Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

Download PDF
ID 683297
Date 12/21/2020
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Arria® V GZ Hard IP for PCI Express 3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design 4. Parameter Settings 5. Interfaces and Signal Descriptions 6. Registers 7. Interrupts 8. Error Handling 9. PCI Express Protocol Stack 10. Transaction Layer Protocol (TLP) Details 11. Throughput Optimization 12. Design Implementation 13. Additional Features 14. Hard IP Reconfiguration 15. Transceiver PHY IP Reconfiguration 16. Testbench and Design Example 17. Debugging A. Lane Initialization and Reversal B. Document Revision History
1. Datasheet x
1.1. Arria® V GZ Avalon-ST Interface for PCIe Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Configurations 1.5. Avalon-ST Example Designs 1.6. Debug Features 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.1. Arria® V GZ Avalon-ST Interface for PCIe Datasheet x
1.1.1. Features
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Arria® V GZ Hard IP for PCI Express x
2.1. Qsys Design Flow
2.1. Qsys Design Flow x
2.1.1. Generating the Testbench 2.1.2. Simulating the Example Design 2.1.3. Generating Synthesis Files 2.1.4. Understanding the Files Generated 2.1.5. Understanding Simulation Log File Generation 2.1.6. Understanding Physical Placement of the PCIe IP Core 2.1.7. Compiling the Design in the Qsys Design Flow 2.1.8. Modifying the Example Design 2.1.9. Using the IP Catalog To Generate Your Arria® V GZ Hard IP for PCI Express as a Separate Component
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design x
3.1. Copying the Configuration Space Bypass Mode Example Design 3.2. Generating the Qsys System 3.3. Simulating the Example Design
3.2. Generating the Qsys System x
3.2.1. Generating Synthesis Files 3.2.2. Understanding the Generated Files 3.2.3. Understanding Simulation Log File Generation
3.3. Simulating the Example Design x
3.3.1. Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface 3.3.2. Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface 3.3.3. Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface 3.3.4. Partial Transcript for Configuration Space Bypass Simulation
4. Parameter Settings x
4.1. System Settings 4.2. Base Address Register (BAR) and Expansion ROM Settings 4.3. Base and Limit Registers for Root Ports 4.4. Device Identification Registers 4.5. PCI Express and PCI Capabilities Parameters 4.6. Vendor Specific Extended Capability (VSEC) 4.7. PHY Characteristics
4.5. PCI Express and PCI Capabilities Parameters x
4.5.1. PCI Express and PCI Capabilities 4.5.2. Error Reporting 4.5.3. Link Capabilities 4.5.4. MSI and MSI-X Capabilities 4.5.5. Slot Capabilities 4.5.6. Power Management
5. Interfaces and Signal Descriptions x
5.1. Clock Signals 5.2. Reset, Status, and Link Training Signals 5.3. ECRC Forwarding 5.4. Error Signals 5.5. Interrupts for Endpoints 5.6. Interrupts for Root Ports 5.7. Completion Side Band Signals 5.8. Configuration Space Bypass Mode Interface Signals 5.9. Parity Signals 5.10. LMI Signals 5.11. Transaction Layer Configuration Space Signals 5.12. Hard IP Reconfiguration Interface 5.13. Power Management Signals 5.14. Physical Layer Interface Signals
5.11. Transaction Layer Configuration Space Signals x
5.11.1. Configuration Space Register Access Timing 5.11.2. Configuration Space Register Access
5.14. Physical Layer Interface Signals x
5.14.1. Transceiver Reconfiguration 5.14.2. Serial Data Signals 5.14.3. PIPE Interface Signals 5.14.4. Test Signals
5.14.2. Serial Data Signals x
5.14.2.1. Physical Layout of Hard IP in Arria V GZ Devices 5.14.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. CvP Registers 6.7. Uncorrectable Internal Error Mask Register 6.8. Uncorrectable Internal Error Status Register 6.9. Correctable Internal Error Mask Register 6.10. Correctable Internal Error Status Register
7. Interrupts x
7.1. Interrupts for Endpoints 7.2. Interrupts for Root Ports
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
9. PCI Express Protocol Stack x
9.1. Top-Level Interfaces 9.2. Transaction Layer 9.3. Data Link Layer 9.4. Physical Layer
9.1. Top-Level Interfaces x
9.1.1. Avalon-ST Interface 9.1.2. Clocks and Reset 9.1.3. Local Management Interface (LMI Interface) 9.1.4. Hard IP Reconfiguration 9.1.5. Transceiver Reconfiguration 9.1.6. Interrupts 9.1.7. PIPE
9.2. Transaction Layer x
9.2.1. Configuration Space 9.2.2. Configuration Space Bypass Mode
10. Transaction Layer Protocol (TLP) Details x
10.1. Supported Message Types 10.2. Transaction Layer Routing Rules 10.3. Receive Buffer Reordering
10.1. Supported Message Types x
10.1.1. INTX Messages 10.1.2. Power Management Messages 10.1.3. Error Signaling Messages 10.1.4. Locked Transaction Message 10.1.5. Slot Power Limit Message 10.1.6. Vendor-Defined Messages 10.1.7. Hot Plug Messages
10.3. Receive Buffer Reordering x
10.3.1. Using Relaxed Ordering
11. Throughput Optimization x
11.1. Throughput of Posted Writes 11.2. Throughput of Non-Posted Reads
12. Design Implementation x
12.1. Making Analog QSF Assignments Using the Assignment Editor 12.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 12.3. Recommended Reset Sequence to Avoid Link Training Issues 12.4. SDC Timing Constraints
13. Additional Features x
13.1. Configuration over Protocol (CvP) 13.2. Autonomous Mode 13.3. ECRC
13.2. Autonomous Mode x
13.2.1. Enabling Autonomous Mode 13.2.2. Enabling CvP Initialization
13.3. ECRC x
13.3.1. ECRC on the RX Path 13.3.2. ECRC on the TX Path
15. Transceiver PHY IP Reconfiguration x
15.1. Connecting the Transceiver Reconfiguration Controller IP Core 15.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
16. Testbench and Design Example x
16.1. Endpoint Testbench 16.2. Root Port Testbench 16.3. Test Driver Module 16.4. Root Port Design Example 16.5. Root Port BFM Overview 16.6. BFM Procedures and Functions 16.7. Setting Up Simulation
16.1. Endpoint Testbench x
16.1.1. Endpoint Testbench for SR-IOV
16.5. Root Port BFM Overview x
16.5.1. BFM Memory Map 16.5.2. Configuration Space Bus and Device Numbering 16.5.3. Configuration of Root Port and Endpoint 16.5.4. Issuing Read and Write Transactions to the Application Layer
16.6. BFM Procedures and Functions x
16.6.1. ebfm_barwr Procedure 16.6.2. ebfm_barwr_imm Procedure 16.6.3. ebfm_barrd_wait Procedure 16.6.4. ebfm_barrd_nowt Procedure 16.6.5. ebfm_cfgwr_imm_wait Procedure 16.6.6. ebfm_cfgwr_imm_nowt Procedure 16.6.7. ebfm_cfgrd_wait Procedure 16.6.8. ebfm_cfgrd_nowt Procedure 16.6.9. BFM Configuration Procedures 16.6.10. BFM Shared Memory Access Procedures 16.6.11. BFM Log and Message Procedures 16.6.12. Verilog HDL Formatting Functions
16.6.9. BFM Configuration Procedures x
16.6.9.1. ebfm_cfg_rp_ep Procedure 16.6.9.2. ebfm_cfg_decode_bar Procedure
16.6.10. BFM Shared Memory Access Procedures x
16.6.10.1. Shared Memory Constants 16.6.10.2. shmem_write Task 16.6.10.3. shmem_read Function 16.6.10.4. shmem_display Verilog HDL Function 16.6.10.5. shmem_fill Procedure 16.6.10.6. shmem_chk_ok Function
16.6.11. BFM Log and Message Procedures x
16.6.11.1. ebfm_display Verilog HDL Function 16.6.11.2. ebfm_log_stop_sim Verilog HDL Function 16.6.11.3. ebfm_log_set_suppressed_msg_mask Task 16.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 16.6.11.5. ebfm_log_open Verilog HDL Function 16.6.11.6. ebfm_log_close Verilog HDL Function
16.6.12. Verilog HDL Formatting Functions x
16.6.12.1. himage1 16.6.12.2. himage2 16.6.12.3. himage4 16.6.12.4. himage8 16.6.12.5. himage16 16.6.12.6. dimage1 16.6.12.7. dimage2 16.6.12.8. dimage3 16.6.12.9. dimage4 16.6.12.10. dimage5 16.6.12.11. dimage6 16.6.12.12. dimage7
16.7. Setting Up Simulation x
16.7.1. Changing Between Serial and PIPE Simulation 16.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 16.7.3. Viewing the Important PIPE Interface Signals 16.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 16.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 16.7.6. Changing between the Hard and Soft Reset Controller
17. Debugging x
17.1. Hardware Bring-Up Issues 17.2. Link Training 17.3. Use Third-Party PCIe Analyzer 17.4. BIOS Enumeration Issues
17.2. Link Training x
17.2.1. Debugging Link that Fails To Reach L0 17.2.2. Link Hangs in L0 State
B. Document Revision History x
B.1. Document Revision History of the Arria® V GZ Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Arria® V GZ Hard IP for PCI Express
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
4. Parameter Settings
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Transceiver PHY IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Lane Initialization and Reversal
B. Document Revision History

B.1. Document Revision History of the Arria® V GZ Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide

Date

Version

Changes Made

2020.12.21 18.0 Fixed broken links.
2020.06.02 18.0

Changed the clock associated with the tl_cfg_add[3:0] and tl_cfg_sts[52:0] to coreclkout_hip in the Transaction Layer Configuration Space Signals section.

Updated the Configuration Space Register Access Timing section to state that the tl_cfg_add[3:0] and tl_cfg_ctl[31:0] update every eight coreclkout_hip cycles.

2020.03.19 18.0 Updated reset sequence and descriptions in Reset and Clocks to show that reset_status is the output that can be used to drive the reset of the Application Layer logic.
2019.12.20 18.0 Changed the name of the 1A state for the ltssmstate[4:0] signals to Recovery.Speed to follow the PCIe Specifications.
2019.12.02 18.0 Changed the description of the parameter BAR Size for Legacy Endpoint variants from 6 Bytes - 4 KB to 16 Bytes - 4 KB (for I/O space BARs).
2019.10.09 18.0 Added the 1F state (Recovery.Equalization, Done) for ltssmstate[4:0].
2019.05.22 18.0 Added a note clarifying that the 24-bit Class Code register consists of three 8-bit fields: Base Class Code, Sub-Class Code and Programming Interface.
2019.05.03 18.0 Updated the diagram for the reset sequence of the Hard IP for PCI Express IP Core and Application Layer to reflect the real behavior of reset_status.
2019.01.18 18.0

Removed the High and Maximum options for the RX buffer allocation parameter because they are not supported.

Changed the readyLatency of the RX interface to 3 cycles.

2018.12.28 18.0 Added a note clarifying that the IP core can support up to 256 tags only when in Configuration Bypass mode.
2018.09.11 18.0 Updated the description for pld_clk in the Clock Signals and Clock Summary sections. Also updated the clock domain in the timing diagrams in the Data Alignment and Timing for the 64-Bit Avalon-ST TX Interface section.
2018.08.13 18.0 Added the step to invoke Vsim to the instructions for running a ModelSim simulation.
2018.05.07 18.0

Replaced all references to Intel® Cyclone® 10 with Intel® Cyclone® 10 GX.

2017.10.14 17.1

Corrected typo: added optional parameter to invert the RX polarity, not the TX polarity.

2017.10.06 17.1 Made the following changes to the user guide:
  • Added support for Intel® Cyclone® 10 GX devices.
  • Removed the Getting Started with the Hard IP for PCI Express with the Avalon-ST Interface. The PCIe Quick Start Guide which downloads to hardware replaces it.
  • Corrected signal name, tx_cred_cons_sel should be tx_cons_cred_sel.

  • Revised the Testbench and Design Example chapter. Although the functions and tasks that implement the testbench have not changed, the organization of these functions and task in files is entirely different than in earlier device families.

  • Fixed minor errors and typos.
2017.05.12 17.0

Made the following changes to the user guide:

  • Revised discussion of Application Layer Interrupt Handler Module to include legacy interrupt generation.
  • Corrected the definition of Enable Common Clock Configuration (for lower latency).
  • Corrected Feature Comparison for all Hard IP for PCI Express IP Cores table. Out-of-order Completions are not supported transparently for the Avalon-MM with DMA interface.
  • Corrected default values for the Uncorrectable Internal Error Mask Register and Correctable Internal Error Mask Register registers.
  • Restored Configuration Space Register Access section.
  • Corrected minor errors and typos.
2016.10.31 16.1

Made the following changes to the user guide:

  • Added PCIe bifurcation to the Feature Comparison for all Hard IP for PCI Express IP Cores table. PCI bifurcation is not supported.
  • Corrected description of tl_cfg* bus. Provided sample RTL code to show how sample tl_cfg_ctl.Corrected tl_cfg_ctl Timing diagram.
  • Added instructions for turning on autonomous mode in the Quartus Prime software.
2016.05.02 16.0 Made the following changes:
  • The Quick Start Guide no longer supports the DMA design example.
  • Added figure for TX 3-dword header with qword aligned data.
  • Added Gen3 x2 128-bit interface with 125 MHz clock to the coreclkout_hip Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and Application Layer Interface Widths table.
  • Added statement that the testbench can only simulate a single Endpoint or Root Port at a time.
  • Enhanced statements covering the deficiencies of the Intel-provided testbench.
  • Added simulation support for Gen3 PIPE mode using the ModelSim, VCS, and NCSim simulators.
  • Corrected minor errors and typos.
2015.11.30 15.1 Made the following changes:
  • Added definition for tx_fifo_empty signal.
  • Corrected the frequency range in the Clock Summary table.
  • Added description of the Altera PCIe Reconfig Driver in the Connecting the Transceiver Reconfiguration Controller IP Core topic.
  • Added a FAQ chapter.
  • Added figure illustrating data alignment for the TX 3-dword header with qword aligned address.
  • Added TLP Support Comparison for all Hard IP for PCI Express IP Cores in Datasheet chapter.
  • Added new topic on Autonomous Mode in which the Hard IP for PCI Express begins operation when the periphery configuration completes.
  • Added create_clock to the SDC Timing Constraints topic in the Design Implementation chapter.
2014.12.15 14.1 Made the following changes to the user guide:
  • Added simulation log file, altpcie_monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory. Generation of the log file requires the following simulation file, <install_dir>altera/altera_pcie/altera_pcie_<dev>_hip/altpcie_monitor_<dev>_dlhip_sim.sv, that was not present in earlier releases of the Quartus II software.
  • Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
  • Corrected bit definitions for CvP Status register.
  • Updated definition of CVP_NUMCLKS in the CvP Mode Control register.
  • Added definitions for test_in[2], test_in[6] and test_in[7].
  • Added 2 additional SDC timing constraints for Gen3 in SDC Timing Constraints Required for the Intel® Arria® 10 Hard IP for PCIe and Design Example.
2014.06.30 14.0

Added the following new features to the Intel® Arria® 10 Hard IP for PCI Express:

  • Added parameters to enable 256 completion tags with completion tag checking performed in Application Layer.
  • Added simulation log file, altpcie_monitor_sv_dlhip_tlp_file_log.log, that is automatically generated in your simulation directory. To simulation in the Quartus II 14.0 software release, you must regenerate your IP core to create the supporting monitor file the generates altpcie_monitor_sv_dlhip_tlp_file_log.log. Refer to Understanding Simulation Dump File Generation for details.
  • Added support for new parameter,User ID register from the Vendor Specific Extended Capability, for Endpoints.
  • Added parameter to create a reset pulse at power-up when the soft reset controller is enabled.
  • Simulation support for Phase 2 and Phase 3 equalization when requested by third-party BFM.
  • Increased size of lmi_addr to 15 bits.

Made the following changes to the user guide:

  • Added Next Steps in Creating a Design for PCI Express to Datasheet chapter.
  • Corrected frequency range for hip_reconfig_clk. It should be 100-125 MHz.
  • Corrected Maximum payload size values listed in Reconfigurable Read-Only Registers table. The maximum size is 2048 bytes.
  • Enhanced definition of Device ID and Sub-system Vendor ID to say that these registers are only valid in the Type 0 (Endpoint) Configuration Space.
  • Changed the default reset controller settings. By default Gen1 devices use the Hard Reset Controller. Gen2 and Gen3 devices use the Soft Reset Controller.
  • Corrected frequencies of pclk in Reset and Clocks chapter.
  • Removed txdatavalid0 signal from the PIPE interface. This signal is not available.
  • Removed references to the MegaWizard® Plug-In Manager. In 14.0 the IP Parameter Editor Powered by Platform Designer has replaced the MegaWizard Plug-In Manager.
  • Made the following changes to the timing diagram, Hard IP Reconfiguration Bus Timing of Read-Only Registers:
    • Added hip_reconfig_rst_n.
    • Changed timing of avmm_rdata[15:0]. Valid data returns 4 cycles after avmm_rd.
  • Added link to a Knowledge Base Solution that shows how to observe the test_in bus for debugging.
  • Removed optional 125 MHz reference clock frequency. This option has not been tested extensively in hardware.
  • Corrected channel placement diagrams for Gen3 x2 and Gen3 x4. The CMU PLL should be shown in the Channel 4 location. For Gen3 x2, the second data channel is Ch1. For Gen3 x4, the data channels are Ch0 - Ch3.
  • Corrected figure showing physical placement of PCIe Hard IP modules for Arria V GZ devices.
  • Added definition for test_in[6] and link to Knowledge Base Solution on observing the PIPE interface signals on the test_out bus.
  • Removed references to Gen2 x1 62.5 MHz configuration. This configuration is not supported.
  • Removed statement that Gen1 and Gen2 designs do not require transceiver reconfiguration. Gen1 and Gen2 designs may require transceiver reconfiguration to improve signal quality.
  • Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure. The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCIe Reconfig Driver.
  • Removed soft reset controller .sdc constraints from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altpcied_<dev>.sdc example. These constraints are now in a separate file in the synthesis/submodules directory.
  • Updated Power Supply Voltage Requirements table.
  • For Arria V GZ and Stratix V devices, corrected channel placement diagrams for x8. Both Gen3 Channel Placement Using the CMU and ATX PLLs and Gen1 and Gen2 Channel Placement Using the ATX PLL show the ATX PLL1 in bank 1 being used. However, ATX PLL 1 in bank 0 is actually used.
2013.12.20 13.1 Made the following changes:
  • Divided user guide into 3 separate documents by interface type.
  • Added Design Implementation chapter.
  • In the Debugging chapter, removed section explaining how to turn off the scrambler for Gen3 because it does not work.
  • In the Debugging chapter, corrected filename that you must change to reduce counter values in simulation.
  • In Getting Started with the Avalon-MM Hard IP for PCI Express chapter, corrected connects for the Transceiver Reconfiguration Controller IP Core reset signal, alt_xcvr_reconfig_0 mgmt_rst_reset. This reset input connects to clk_0 clk_reset.
  • In Transaction Layer Routing Rules and Programming Model for Avalon-MM Root Port added the fact that Type 0 Configuration Requests sent to the Root Port are not filtered by the device number. Application Layer software must filter out requests for device number greater than 0.
  • Added illustration showing the location of the Hard IP Cores in the Intel® Arria® 10 devices.
  • Added limitation for rxm_irq_<n>[<m>:0]when interrupts are received on consecutive cycles.
  • Corrected description of cfg_prm_cmr. It is the Base/Primary Command register for the PCI Configuration Space.
  • Revised channel placement illustrations.

2013.05.06

13.0

  • Added support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions
  • Added preliminary support for a Avalon-MM 256-Bit Hard IP for PCI Express that is capable of running at the Gen3 ×8 data rate. This new IP Core. Refer to the Avalon-MM 256-Bit Hard IP for PCI Express User Guide for more information.
  • Added Gen3 PIPE simulation support.
  • Added support for 64-bit address in the Avalon-MM Hard IP for PCI Express IP Core, making address translation unnecessary
  • Added instructions for running the Single Dword variant.
  • Timing models are now final.
  • Updated the definition of refclk to include constraints when CvP is enabled.
  • Added section covering clock connectivity for reconfiguration when CvP is enabled.
  • Corrected access field in Root Port TLP Data registers.
  • Added Getting Started chapter for Configuration Space Bypass mode.
  • Added signal and register descriptions for the Gen3 PIPE simulation.
  • Added 64-bit addressing for the Avalon-MM IP Cores for PCI Express.
  • Changed descriptions of rx_st_err[1:0], tx_st_err[1:0], rx_st_valid[1:0], and tx_st_valid[1:0] buses. Bit 1 is not used.
  • Corrected definitions of RP_RXCPL_STATUS.SOP and RP_RXCPL_STATUS.EOP bits. SOP is 0x2010, bit[0] and EOP is 0x2010, bit[1].
  • Improved explanation of relaxed ordering of transactions and provided examples.
  • Revised discussion of Transceiver Reconfiguration Controller IP Core. Offset cancellation is not required for Gen1 or Gen2 operation.

2011.07.30

11.01

Corrected typographical errors.

2011.05.06

11.0

First release.

Level Two Title