Intel® Quartus® Prime Pro Edition Settings File Reference Manual

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ID 683296
Date 4/04/2022
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Document Table of Contents x
Intel® Quartus® Prime Pro Edition Settings File Reference Manual
Intel® Quartus® Prime Pro Edition Settings File Reference Manual x
Advanced I/O Timing Assignments Analysis & Synthesis Assignments Assembler Assignments Classic Timing Assignments Compiler Assignments Design Assistant Assignments Design Partition Assignments EDA Netlist Writer Assignments Equivalence Checker Assignments Fitter Assignments Logic Generation Assignments Netlist Viewer Assignments Pin & Location Assignments Power Estimation Assignments Programmer Assignments Project-Wide Assignments Retimer Assignments Retimer Fast Forward Assignments Signal Probe Assignments Signal Tap Assignments Simulator Assignments
Advanced I/O Timing Assignments x
BOARD_MODEL_EBD_FAR_END BOARD_MODEL_EBD_FILE_NAME BOARD_MODEL_EBD_SIGNAL_NAME BOARD_MODEL_FAR_C BOARD_MODEL_FAR_DIFFERENTIAL_R BOARD_MODEL_FAR_PULLDOWN_R BOARD_MODEL_FAR_PULLUP_R BOARD_MODEL_FAR_SERIES_R BOARD_MODEL_NEAR_C BOARD_MODEL_NEAR_DIFFERENTIAL_R BOARD_MODEL_NEAR_PULLDOWN_R BOARD_MODEL_NEAR_PULLUP_R BOARD_MODEL_NEAR_SERIES_R BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH BOARD_MODEL_NEAR_TLINE_LENGTH BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH BOARD_MODEL_TERMINATION_V BOARD_MODEL_TLINE_C_PER_LENGTH BOARD_MODEL_TLINE_LENGTH BOARD_MODEL_TLINE_L_PER_LENGTH OUTPUT_IO_TIMING_ENDPOINT OUTPUT_IO_TIMING_FAR_END_VMEAS OUTPUT_IO_TIMING_NEAR_END_VMEAS
Analysis & Synthesis Assignments x
ADV_NETLIST_OPT_ALLOWED ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP AGGRESSIVE_MUX_AREA_OPTIMIZATION ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ALLOW_CHILD_PARTITIONS ALLOW_MAX_FANOUT_SPLITTING_FOR_ASYNCHRONOUS_FANOUT ALLOW_POWER_UP_DONT_CARE ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALLOW_SYNCH_CTRL_USAGE ALTERA_A10_IOPLL_BOOTSTRAP AUTO_CLOCK_ENABLE_RECOGNITION AUTO_DSP_RECOGNITION AUTO_ENABLE_SMART_COMPILE AUTO_OPEN_DRAIN_PINS AUTO_PARALLEL_SYNTHESIS AUTO_RAM_RECOGNITION AUTO_RESOURCE_SHARING AUTO_ROM_RECOGNITION AUTO_SHIFT_REGISTER_RECOGNITION BARRELSHIFTER_CARRY_CHAIN_PACKING BLOCK_DESIGN_NAMING BOARD DEVICE_FILTER_PACKAGE DEVICE_FILTER_PIN_COUNT DEVICE_FILTER_SPEED_GRADE DEVICE_FILTER_VOLTAGE DISABLE_DSP_NEGATE_INFERENCING DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES DISABLE_REGISTER_POWER_UP_INITIALIZATION DONT_MERGE_REGISTER DSE_SYNTH_EXTRA_EFFORT_MODE DSP_BLOCK_BALANCING DUPLICATE_HIERARCHY_DEPTH EDA_DESIGN_ENTRY_SYNTHESIS_TOOL EDA_INPUT_DATA_FORMAT EDA_INPUT_GND_NAME EDA_INPUT_VCC_NAME EDA_LMF_FILE EDA_RUN_TOOL_AUTOMATICALLY EDA_SHOW_LMF_MAPPING_MESSAGES EDA_VHDL_LIBRARY ENABLE_FORMAL_VERIFICATION ENABLE_FPGA_TAMPER_DETECTION ENABLE_STATE_MACHINE_INFERENCE ENABLE_SV_STATIC_ASSERTIONS ENABLE_VHDL_STATIC_ASSERTIONS FAMILY FORCE_CLOCK_ENABLE_INFERENCE FORCE_SYNCH_CLEAR FRACTAL_SYNTHESIS GROUP_IDENTICAL_HIERARCHIES HDL_INITIAL_FANOUT_LIMIT HDL_MESSAGE_LEVEL HDL_MESSAGE_OFF HDL_MESSAGE_ON HPS_PARTITION IGNORE_GLOBAL_BUFFERS IGNORE_LCELL_BUFFERS IGNORE_MAX_FANOUT_ASSIGNMENTS IGNORE_REGISTER_POWER_UP_INITIALIZATION IGNORE_SOFT_BUFFERS IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF IMPLEMENT_AS_CLOCK_ENABLE IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL INFER_RAMS_FROM_RAW_LOGIC INIT_ENUM_TO_X IP_SEARCH_PATHS MAX_BALANCING_DSP_BLOCKS MAX_FANOUT MAX_FANOUT_FOR_SYNCH_CTRL MAX_LABS MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS MAX_RAM_BLOCKS_M4K MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE MUX_RESTRUCTURE NOT_GATE_PUSH_BACK NUMBER_OF_INVERTED_REGISTERS_REPORTED NUMBER_OF_OPTIMIZED_AWAY_HIERARCHIES_REPORTED NUMBER_OF_PROTECTED_REGISTERS_REPORTED NUMBER_OF_REMOVED_REGISTERS_REPORTED NUMBER_OF_SWEPT_NODES_REPORTED OCP_HW_EVAL OPTIMIZATION_TECHNIQUE OPTIMIZE_POWER_DURING_SYNTHESIS PARAMETER PHYSICAL_SHIFT_REGISTER_INFERENCE POWER_UP_LEVEL PRESERVE_FANOUT_FREE_NODE PRESERVE_FANOUT_FREE_WYSIWYG PRESERVE_REGISTER PRESERVE_REGISTER_SYN_ONLY PRPOF_ID QUICK_ELAB_TILE_IP QUICK_ELAB_TILE_IP_PROPERTY RAMSTYLE_ATTRIBUTE RAMSTYLE_ATTRIBUTE_RDW RBCGEN_CRITICAL_WARNING_TO_ERROR REMOVE_DUPLICATE_REGISTERS REMOVE_REDUNDANT_LOGIC_CELLS REPORT_ENTITY_UTILIZATION_TO_ASCII_PRO REPORT_PARAMETER_SETTINGS_PRO REPORT_PARAMETER_SETTINGS_TO_ASCII_PRO REPORT_PR_INITIAL_VALUES_AS_ERROR REPORT_SOURCE_ASSIGNMENTS_PRO REPORT_SOURCE_ASSIGNMENTS_TO_ASCII_PRO RESYNTHESIS_OPTIMIZATION_EFFORT RESYNTHESIS_PHYSICAL_SYNTHESIS RESYNTHESIS_RETIMING SAFE_STATE_MACHINE SAVE_DISK_SPACE SEARCH_PATH SECONDARY_TOP_LEVEL_ENTITY SHIFT_REGISTER_DO_NOT_LEAVE_REGISTER_OUTSIDE SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL SIZE_OF_IGNORED_POWER_UP_REPORT SIZE_OF_LATCH_REPORT SIZE_OF_PR_INITIAL_CONDITIONS_REPORT SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES STATE_MACHINE_PROCESSING STRICT_RAM_RECOGNITION SYNCHRONIZATION_REGISTER_CHAIN_LENGTH SYNTHESIS_AVAILABLE_RESOURCE_MULTIPLIER SYNTHESIS_EFFORT SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER SYNTHESIS_S10_MIGRATION_CHECKS SYNTH_CLOCK_MUX_PROTECTION SYNTH_GATED_CLOCK_CONVERSION SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK SYNTH_MESSAGE_LEVEL SYNTH_PROTECT_SDC_CONSTRAINT SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM SYNTH_TIMING_DRIVEN_SYNTHESIS TOP_LEVEL_ENTITY UNCONNECTED_OUTPUT_PORT_MESSAGE_LEVEL USER_LIBRARIES USE_AS_EIO_GPIO USE_GENERATED_PHYSICAL_CONSTRAINTS VERILOG_ALLOW_RAM_INFERRED_IN_GENERATE_LOOP VERILOG_CONSTANT_LOOP_LIMIT VERILOG_INPUT_VERSION VERILOG_LMF_FILE VERILOG_MACRO VERILOG_NON_CONSTANT_LOOP_LIMIT VERILOG_SHOW_LMF_MAPPING_MESSAGES VHDL_COND_ANALYSIS_USER_DEFINES_FILE VHDL_INPUT_LIBRARY VHDL_INPUT_VERSION VHDL_LMF_FILE VHDL_SHOW_LMF_MAPPING_MESSAGES
Assembler Assignments x
ANTI_TAMPER_RESPONSE ATTESTATION_ALT_NAME_MANUFACTURER ATTESTATION_ALT_NAME_PRODUCT ATTESTATION_CRL_DISTRIBUTION_POINT ATTESTATION_MODEL_INFO ATTESTATION_RIM_URI_PREFIX ATTESTATION_RIM_URI_SUFFIX ATTESTATION_VENDOR_INFO AUTO_RESTART_CONFIGURATION CLOCK_SOURCE COMPRESSION_MODE CONFIGURATION_CLOCK_DIVISOR CONFIGURATION_CLOCK_FREQUENCY CONVERT_PROGRAMMING_FILES_COMMANDS ENABLE_ADV_SEU_DETECTION ENABLE_AUTONOMOUS_PCIE_HIP ENABLE_FPGA_TAMPER_DEVICE_SELF_KILL ENABLE_FREQUENCY_TAMPER_DETECTION ENABLE_FREQUENCY_TAMPER_DEVICE_SELF_KILL ENABLE_MULTI_AUTHORITY ENABLE_OCT_DONE ENABLE_PARTIAL_RECONFIGURATION_BITSTREAM_ENCRYPTION ENABLE_PR_POF_ID ENABLE_S10_ATTESTATION_COMMANDS ENABLE_TEMPERATURE_TAMPER_DETECTION ENABLE_TEMPERATURE_TAMPER_DEVICE_SELF_KILL ENABLE_VCCL_SDM_VOLTAGE_TAMPER_DETECTION ENABLE_VCCL_VOLTAGE_TAMPER_DETECTION ENABLE_VOLTAGE_TAMPER_DETECTION ENABLE_VOLTAGE_TAMPER_DEVICE_SELF_KILL ENCRYPT_PROGRAMMING_BITSTREAM EPROM_USE_CHECKSUM_AS_USERCODE FREQUENCY_TAMPER_DETECTION_RANGE GENERATE_COMPRESSED_SOF GENERATE_HEX_FILE GENERATE_PMSF_FILES GENERATE_PROGRAMMING_FILES GENERATE_PR_RBF_FILE GENERATE_RBF_FILE GENERATE_TTF_FILE HEXOUT_FILE_COUNT_DIRECTION HEXOUT_FILE_START_ADDRESS HPS_DAP_NO_CERTIFICATE HPS_DAP_SPLIT_MODE HPS_INITIALIZATION HPS_RETAIN_DDR_CONTENT LOW_VOLTAGE_MODE NUMBER_OF_SLAVE_DEVICE ON_CHIP_BITSTREAM_DECOMPRESSION PROGRAMMING_BITSTREAM_ENCRYPTION_CNOC_SCRAMBLING PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT PROGRAMMING_BITSTREAM_ENCRYPTION_UPDATE_RATIO PR_BASE_MSF PR_BASE_SOF PR_SKIP_BASE_CHECK PWRMGT_ADV_CLOCK_DATA_FALL_TIME PWRMGT_ADV_CLOCK_DATA_RISE_TIME PWRMGT_ADV_DATA_HOLD_TIME PWRMGT_ADV_DATA_SETUP_TIME PWRMGT_ADV_FPGA_RELEASE_DELAY PWRMGT_ADV_INITIAL_DELAY PWRMGT_ADV_VOLTAGE_STABLE_DELAY PWRMGT_ADV_VOUT_READING_ERR_MARGIN PWRMGT_BUS_SPEED_MODE PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE PWRMGT_DIRECT_FORMAT_COEFFICIENT_B PWRMGT_DIRECT_FORMAT_COEFFICIENT_M PWRMGT_DIRECT_FORMAT_COEFFICIENT_R PWRMGT_LINEAR_FORMAT_N PWRMGT_PAGE_COMMAND_ENABLE PWRMGT_PAGE_COMMAND_PAYLOAD PWRMGT_SLAVE_DEVICE0_ADDRESS PWRMGT_SLAVE_DEVICE1_ADDRESS PWRMGT_SLAVE_DEVICE2_ADDRESS PWRMGT_SLAVE_DEVICE3_ADDRESS PWRMGT_SLAVE_DEVICE4_ADDRESS PWRMGT_SLAVE_DEVICE5_ADDRESS PWRMGT_SLAVE_DEVICE6_ADDRESS PWRMGT_SLAVE_DEVICE7_ADDRESS PWRMGT_SLAVE_DEVICE_TYPE PWRMGT_TABLE_VERSION PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT PWRMGT_VOLTAGE_OUTPUT_FORMAT QKY_FILE RBF_FILE_GENERATION_FOR_SUPR RELEASE_CLEARS_BEFORE_TRI_STATES RSU_MAX_RETRY_COUNT RUN_CONFIG_CPU_FROM_INT_OSC SECU_OPTION_DISABLE_ALIAS_L1 SECU_OPTION_DISABLE_ENCRYPTION_KEY_IN_BBRAM SECU_OPTION_DISABLE_ENCRYPTION_KEY_IN_EFUSES SECU_OPTION_DISABLE_HPS_DEBUG SECU_OPTION_DISABLE_JTAG SECU_OPTION_DISABLE_PUF_WRAPPED_ENCRYPTION_KEY SECU_OPTION_DISABLE_VIRTUAL_EFUSES SECU_OPTION_FORCE_ENCRYPTION_KEY_UPDATE SECU_OPTION_FORCE_SDM_CLOCK_TO_INT_OSC SECU_OPTION_LOCK_SECURITY_EFUSES STRATIXII_CONFIGURATION_DEVICE STRATIX_JTAG_USER_CODE TEMPERATURE_TAMPER_LOWER_BOUND TEMPERATURE_TAMPER_UPPER_BOUND UNINITIALIZED_RAM_CONTENT_PATTERN USE_ALIAS_L1 USE_CHECKSUM_AS_USERCODE USE_CONFIGURATION_DEVICE VCCL_SDM_VOLTAGE_DIFFERENCE_TRIGGER VCCL_VOLTAGE_DIFFERENCE_TRIGGER VOLTAGE_TAMPER_DETECTION_TRIGGER
Classic Timing Assignments x
ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS CUT_OFF_IO_PIN_FEEDBACK CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS CUT_OFF_READ_DURING_WRITE_PATHS DEFAULT_HOLD_MULTICYCLE EMIF_SOC_PHYCLK_ADVANCE_MODELING ENABLE_HPS_INTERNAL_TIMING FLOW_ENABLE_TIMING_ANALYZER_AFTER_PLAN_STAGE IMPLEMENTS_FREE_RUNNING_CLOCK INPUT_TRANSITION_TIME MAX_CORE_JUNCTION_TEMP MIN_CORE_JUNCTION_TEMP MIN_MTBF_REQUIREMENT NOMINAL_CORE_SUPPLY_VOLTAGE PACKAGE_SKEW_COMPENSATION PLL_EXTERNAL_FEEDBACK_BOARD_DELAY SDC_STATEMENT STA_AUTO_REPORT_SETUP_SUMMARY STA_AUTO_UPDATE_TIMING_NETLIST TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT TIMING_ANALYZER_DO_CCPP_REMOVAL TIMING_ANALYZER_DO_REPORT_CDC_VIEWER TIMING_ANALYZER_DO_REPORT_TIMING TIMING_ANALYZER_MULTICORNER_ANALYSIS TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS TIMING_ANALYZER_REPORT_SCRIPT TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS TIMING_ANALYZER_SIMULTANEOUS_MULTICORNER_ANALYSIS TIMING_ANAYZER_REPORT_WORST_CASE_TIMING_PATHS_SHOW_ROUTING USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
Compiler Assignments x
ALLOW_REGISTER_DUPLICATION ALLOW_REGISTER_MERGING ALLOW_REGISTER_RETIMING OPTIMIZATION_MODE
Design Assistant Assignments x
CLK_RULE_CLKNET_CLKSPINES_THRESHOLD DA_CUSTOM_RULE_FILE DESIGN_ASSISTANT_EXCLUDE DESIGN_ASSISTANT_INCLUDE DRC_DEADLOCK_STATE_LIMIT DRC_DETAIL_MESSAGE_LIMIT DRC_FANOUT_EXCEEDING DRC_GATED_CLOCK_FEED DRC_REPORT_FANOUT_EXCEEDING DRC_REPORT_TOP_FANOUT DRC_TOP_FANOUT DRC_VIOLATION_MESSAGE_LIMIT HARDCOPY_FLOW_AUTOMATION HARDCOPY_NEW_PROJECT_PATH HCPY_CAT HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES HCPY_VREF_PINS
Design Partition Assignments x
ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS AUTOMATIC_DANGLING_PORT_TIEOFF CROSS_BOUNDARY_OPTIMIZATIONS EMPTY ENABLE_LAB_SHARING_WITH_PARENT_PARTITION ENTITY_REBINDING EXPORT_BLOCK_NAME_OBFUSCATION IGNORE_PARTITIONS INCREMENTAL_COMPILATION_EXPORT_FLATTEN INCREMENTAL_COMPILATION_EXPORT_POST_FIT INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH INSERT_BOUNDARY_WIRE_LUTS MERGE_EQUIVALENT_BIDIRS MERGE_EQUIVALENT_INPUTS PARTIAL_RECONFIGURATION_PARTITION PARTITION PARTITION_ALWAYS_USE_QXP_NETLIST PARTITION_ASD_REGION PARTITION_ASD_REGION_ID PARTITION_IGNORE_SOURCE_FILE_CHANGES PARTITION_PRESERVE_HIGH_SPEED_TILES PRESERVE PROPAGATE_CONSTANTS_ON_INPUTS PROPAGATE_INVERSIONS_ON_INPUTS QDB_FILE_PARTITION QDB_PATH REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS RESERVED_CORE RTL_PARAMETER
EDA Netlist Writer Assignments x
EDA_BOARD_BOUNDARY_SCAN_OPERATION EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL EDA_BOARD_DESIGN_SYMBOL_TOOL EDA_BOARD_DESIGN_TIMING_TOOL EDA_BOARD_DESIGN_TOOL EDA_DESIGN_EXTRA_ALTERA_SIM_LIB EDA_DESIGN_INSTANCE_NAME EDA_ENABLE_GLITCH_FILTERING EDA_ENABLE_IPUTF_MODE EDA_EXTRA_ELAB_OPTION EDA_FLATTEN_BUSES EDA_FORCE_GATE_LEVEL_REG_INIT_X EDA_FORMAL_VERIFICATION_ALLOW_RETIMING EDA_FORMAL_VERIFICATION_TOOL EDA_FV_HIERARCHY EDA_GENERATE_POWER_INPUT_FILE EDA_GENERATE_SDF_FOR_POWER EDA_GENERATE_TIMING_CLOSURE_DATA EDA_IBIS_EXTENDED_MODEL_SELECTOR EDA_IBIS_MODEL_SELECTOR EDA_IBIS_MUTUAL_COUPLING EDA_IBIS_SPECIFICATION_VERSION EDA_IPFS_FILE EDA_LAUNCH_CMD_LINE_TOOL EDA_MAP_ILLEGAL_CHARACTERS EDA_NATIVELINK_GENERATE_SCRIPT_ONLY EDA_NATIVELINK_PORTABLE_FILE_PATHS EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT EDA_NATIVELINK_SIMULATION_TEST_BENCH EDA_NETLIST_WRITER_OUTPUT_DIR EDA_RESYNTHESIS_TOOL EDA_RTL_SIMULATION_RUN_SCRIPT EDA_RTL_SIM_MODE EDA_RTL_TEST_BENCH_FILE_NAME EDA_RTL_TEST_BENCH_NAME EDA_RTL_TEST_BENCH_RUN_FOR EDA_SDC_FILE_NAME EDA_SIMULATION_RUN_SCRIPT EDA_SIMULATION_TOOL EDA_TEST_BENCH_DESIGN_INSTANCE_NAME EDA_TEST_BENCH_ENABLE_STATUS EDA_TEST_BENCH_ENTITY_MODULE_NAME EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB EDA_TEST_BENCH_FILE EDA_TEST_BENCH_FILE_NAME EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY EDA_TEST_BENCH_MODULE_NAME EDA_TEST_BENCH_NAME EDA_TEST_BENCH_RUN_FOR EDA_TEST_BENCH_RUN_SIM_FOR EDA_TIME_SCALE EDA_TIMING_ANALYSIS_TOOL EDA_TRUNCATE_LONG_HIERARCHY_PATHS EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY EDA_VHDL_ARCH_NAME EDA_WAIT_FOR_GUI_TOOL_COMPLETION EDA_WRITER_DONT_WRITE_TOP_ENTITY EDA_WRITE_DEVICE_CONTROL_PORTS EDA_WRITE_NODES_FOR_POWER_ESTIMATION
Equivalence Checker Assignments x
EQC_AUTO_BREAK_CONE EQC_AUTO_COMP_LOOP_CUT EQC_AUTO_INVERSION EQC_AUTO_PORTSWAP EQC_AUTO_TERMINATE EQC_BBOX_MERGE EQC_CONSTANT_DFF_DETECTION EQC_DETECT_DONT_CARES EQC_DFF_SS_EMULATION EQC_DUPLICATE_DFF_DETECTION EQC_LVDS_MERGE EQC_MAC_REGISTER_UNPACK EQC_PARAMETER_CHECK EQC_POWER_UP_COMPARE EQC_RAM_REGISTER_UNPACK EQC_RAM_UNMERGING EQC_RENAMING_RULES EQC_RENAMING_RULES_LIST EQC_SET_PARTITION_BB_TO_VCC_GND EQC_SHOW_ALL_MAPPED_POINTS EQC_STRUCTURE_MATCHING EQC_SUB_CONE_REPORT
Fitter Assignments x
ACTIVE_SERIAL_CLOCK ALLOW_ROUTING_TO_PERIPHERY_THROUGH_GLOBAL_NETWORK ALLOW_SEU_FAULT_INJECTION ALLOW_VCCR_VCCT_PER_BANK ALM_REGISTER_PACKING_EFFORT ANTI_TAMPER_RESPONSE_FAILED AUTO_ANALYZE_METASTABILITY AUTO_DELAY_CHAINS AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS AUTO_GLOBAL_CLOCK AUTO_GLOBAL_REGISTER_CONTROLS AUTO_RESERVE_CLKUSR_FOR_CALIBRATION BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS BLOCK_RAM_TO_MLAB_CELL_CONVERSION CDR_BANDWIDTH_PRESET CKN_CK_PAIR CLOCK_REGION Type Device Support Notes Syntax CLOCK_SPINE CONFIGURATION_VCCIO_LEVEL CONVERT_PR_WARNINGS_TO_ERRORS CRC_ERROR_OPEN_DRAIN CURRENT_STRENGTH_NEW CVP_CONFDONE_OPEN_DRAIN CVP_MODE DEVICE DEVICE_INITIALIZATION_CLOCK DEVICE_IO_STANDARD_ALL DEVICE_MIGRATION_LIST DEVICE_TECHNOLOGY_MIGRATION_LIST DQ_GROUP DSP_REGISTER_PACKING DSP_REGISTER_PACKING_LEVEL DUPLICATE_ATOM DUPLICATE_REGISTER DUPLICATE_SYNC_FANIN ENABLE_BUS_HOLD_CIRCUITRY ENABLE_CRC_ERROR_PIN ENABLE_CVP_CONFDONE ENABLE_DEVICE_WIDE_OE ENABLE_DEVICE_WIDE_RESET ENABLE_DSP_REGISTER_UNPACKING ENABLE_ED_CRC_CHECK ENABLE_INFERRED_SHIFT_REG_COUNTER_DUPLICATION ENABLE_INIT_DONE_OUTPUT ENABLE_INTERMEDIATE_SNAPSHOTS ENABLE_NCEO_OUTPUT ENABLE_PR_PINS ENABLE_TIME_BORROWING_OPTIMIZATION ENABLE_UNUSED_RX_CLOCK_WORKAROUND ERROR_CHECK_FREQUENCY_DIVISOR EXCLUSIVE_IO_GROUP FINAL_PLACEMENT_OPTIMIZATION FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN FITTER_DENSITY_PACKING_EFFORT FITTER_EARLY_RETIMING FITTER_EFFORT FLEX10K_MAX_PERIPHERAL_OE FORCE_CONFIGURATION_VCCIO GLOBAL_PLACEMENT_EFFORT GLOBAL_SIGNAL GNDIO_CURRENT_1PT8V GNDIO_CURRENT_2PT5V GNDIO_CURRENT_GTL GNDIO_CURRENT_GTL_PLUS GNDIO_CURRENT_LVCMOS GNDIO_CURRENT_LVTTL GNDIO_CURRENT_PCI GNDIO_CURRENT_SSTL2_CLASS1 GNDIO_CURRENT_SSTL2_CLASS2 GNDIO_CURRENT_SSTL3_CLASS1 GNDIO_CURRENT_SSTL3_CLASS2 GXB_0PPM_CORECLK HPS_COLD_RESET_PIN_MODE HPS_WARM_RESET_PIN_MODE HSSI_PARAMETER IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS IGNORE_SDC_CONSTRAINTS_FOR_REGISTER_PACKING INIT_DONE_OPEN_DRAIN INPUT_DELAY_CHAIN INPUT_TERMINATION INTERNAL_SCRUBBING IO_12_LANE_INPUT_DATA_DELAY_CHAIN IO_12_LANE_INPUT_STROBE_DELAY_CHAIN IO_MAXIMUM_TOGGLE_RATE IO_PARTITION_PLACEMENT IO_STANDARD LVDS_DIRECT_LOOPBACK_MODE MACRO_HEAD MACRO_MEMBER MATCH_PLL_COMPENSATION_CLOCK MIGRATION_DEVICES MINIMUM_SEU_INTERVAL NCEO_OPEN_DRAIN NUMBER_OF_EXAMPLE_NODES_REPORTED OE_DELAY_CHAIN OPTIMIZE_FOR_METASTABILITY OPTIMIZE_HOLD_TIMING OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING OPTIMIZE_MULTI_CORNER_TIMING OPTIMIZE_PERSONA_ROUTABILITY OPTIMIZE_POWER_DURING_FITTING OPTIMIZE_TIMING OUTPUT_DELAY_CHAIN OUTPUT_PIN_LOAD OUTPUT_TERMINATION PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION PERIPH_FITTER_SCRIPT PERIPH_REPORT_SCRIPT PHYSICAL_RAM_RPT_MAX_ROW PHYSICAL_SYNTHESIS PLACEMENT_EFFORT_MULTIPLIER PLL_AUTO_RESET PLL_BANDWIDTH_PRESET PLL_COMPENSATION_MODE PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING PRESERVE_UNUSED_XCVR_CHANNEL PRIORITY_SEU_AREA PROGRAMMABLE_DEEMPHASIS PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES PROGRAMMABLE_POWER_TECHNOLOGY_SETTING PROGRAMMABLE_PREEMPHASIS PROGRAMMABLE_VOD PR_DONE_OPEN_DRAIN PR_ERROR_OPEN_DRAIN PR_PINS_OPEN_DRAIN PR_READY_OPEN_DRAIN PR_SECURITY_VALIDATION PUD_CTRL QII_AUTO_PACKED_REGISTERS RECEIVER_EQUALIZATION RELATIVE_NEUTRON_FLUX REQUIRE_PLL_INITIALIZATION_CLOCK RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP RESERVE_AVST_CLK_AFTER_CONFIGURATION RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION RESERVE_AVST_VALID_AFTER_CONFIGURATION RESERVE_DATA0_AFTER_CONFIGURATION RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION RESERVE_FLEXIBLE_CLOCK_NETWORK RESERVE_PR_PINS RESERVE_ROUTING_OUTPUT_FLEXIBILITY ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ROUTER_EFFORT_MULTIPLIER ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ROUTER_REGISTER_DUPLICATION ROUTER_TIMING_OPTIMIZATION_LEVEL RZQ_GROUP SCHMITT_TRIGGER SDM_DIRECT_TO_FACTORY_IMAGE SDM_PCIE_CALIB_START SEED SEU_FIT_REPORT SHIFT_REG_TO_RAM_INFERENCE_MIN_INPUT_REG_EXCLUDED SHIFT_REG_TO_RAM_INFERENCE_MIN_OUTPUT_REG_EXCLUDED SLEW_RATE SLOW_SLEW_RATE STRATIXV_CONFIGURATION_SCHEME SYNCHRONIZER_IDENTIFICATION SYNCHRONIZER_TOGGLE_RATE TERMINATION_CONTROL_BLOCK TREAT_BIDIR_AS_OUTPUT TRI_STATE_SPI_PINS UNFORCE_MERGE_PLL UNUSED_IO_BANK_VOLTAGE UNUSED_TSD_PINS_GND USE_ADDITIONAL_QSPI_FLASH USE_ANTI_TAMPER USE_AS_3V_GPIO USE_CONF_DONE USE_CVP_CONFDONE USE_DATA_UNLOCK USE_HPS_COLD_RESET USE_HPS_WARM_RESET USE_INIT_DONE USE_NCATTRIP USE_PWRMGT_ALERT USE_PWRMGT_SCL USE_PWRMGT_SDA USE_SEU_ERROR USE_TAMPER_DETECT USE_UIB_CATTRIP VCCIO_CURRENT_1PT8V VCCIO_CURRENT_2PT5V VCCIO_CURRENT_GTL VCCIO_CURRENT_GTL_PLUS VCCIO_CURRENT_LVCMOS VCCIO_CURRENT_LVTTL VCCIO_CURRENT_PCI VCCIO_CURRENT_SSTL2_CLASS1 VCCIO_CURRENT_SSTL2_CLASS2 VCCIO_CURRENT_SSTL3_CLASS1 VCCIO_CURRENT_SSTL3_CLASS2 VERIFIED_GRAY_CODED_BUS_DESTINATIONS VID_OPERATION_MODE VREF_MODE WEAK_PULL_DOWN_RESISTOR WEAK_PULL_UP_DN_SEL WEAK_PULL_UP_RESISTOR WIRELUT_REMOVAL_HOLD_GUARD_BAND WIRELUT_REMOVAL_SETUP_GUARD_BAND XCVR_A10_REFCLK_TERM_TRISTATE XCVR_A10_RX_ADP_CTLE_ACGAIN_4S XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL XCVR_A10_RX_ADP_DFE_FXTAP1 XCVR_A10_RX_ADP_DFE_FXTAP10 XCVR_A10_RX_ADP_DFE_FXTAP10_SGN XCVR_A10_RX_ADP_DFE_FXTAP11 XCVR_A10_RX_ADP_DFE_FXTAP11_SGN XCVR_A10_RX_ADP_DFE_FXTAP2 XCVR_A10_RX_ADP_DFE_FXTAP2_SGN XCVR_A10_RX_ADP_DFE_FXTAP3 XCVR_A10_RX_ADP_DFE_FXTAP3_SGN XCVR_A10_RX_ADP_DFE_FXTAP4 XCVR_A10_RX_ADP_DFE_FXTAP4_SGN XCVR_A10_RX_ADP_DFE_FXTAP5 XCVR_A10_RX_ADP_DFE_FXTAP5_SGN XCVR_A10_RX_ADP_DFE_FXTAP6 XCVR_A10_RX_ADP_DFE_FXTAP6_SGN XCVR_A10_RX_ADP_DFE_FXTAP7 XCVR_A10_RX_ADP_DFE_FXTAP7_SGN XCVR_A10_RX_ADP_DFE_FXTAP8 XCVR_A10_RX_ADP_DFE_FXTAP8_SGN XCVR_A10_RX_ADP_DFE_FXTAP9 XCVR_A10_RX_ADP_DFE_FXTAP9_SGN XCVR_A10_RX_ADP_VGA_SEL XCVR_A10_RX_EQ_BW_SEL XCVR_A10_RX_EQ_DC_GAIN_TRIM XCVR_A10_RX_LINK XCVR_A10_RX_ONE_STAGE_ENABLE XCVR_A10_RX_TERM_SEL XCVR_A10_TX_COMPENSATION_EN XCVR_A10_TX_LINK XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T XCVR_A10_TX_SLEW_RATE_CTRL XCVR_A10_TX_TERM_SEL XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL XCVR_A10_TX_XTX_PATH_ANALOG_MODE XCVR_C10_REFCLK_TERM_TRISTATE XCVR_C10_RX_ADP_CTLE_ACGAIN_4S XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL XCVR_C10_RX_ADP_DFE_FXTAP1 XCVR_C10_RX_ADP_DFE_FXTAP10 XCVR_C10_RX_ADP_DFE_FXTAP10_SGN XCVR_C10_RX_ADP_DFE_FXTAP11 XCVR_C10_RX_ADP_DFE_FXTAP11_SGN XCVR_C10_RX_ADP_DFE_FXTAP2 XCVR_C10_RX_ADP_DFE_FXTAP2_SGN XCVR_C10_RX_ADP_DFE_FXTAP3 XCVR_C10_RX_ADP_DFE_FXTAP3_SGN XCVR_C10_RX_ADP_DFE_FXTAP4 XCVR_C10_RX_ADP_DFE_FXTAP4_SGN XCVR_C10_RX_ADP_DFE_FXTAP5 XCVR_C10_RX_ADP_DFE_FXTAP5_SGN XCVR_C10_RX_ADP_DFE_FXTAP6 XCVR_C10_RX_ADP_DFE_FXTAP6_SGN XCVR_C10_RX_ADP_DFE_FXTAP7 XCVR_C10_RX_ADP_DFE_FXTAP7_SGN XCVR_C10_RX_ADP_DFE_FXTAP8 XCVR_C10_RX_ADP_DFE_FXTAP8_SGN XCVR_C10_RX_ADP_DFE_FXTAP9 XCVR_C10_RX_ADP_DFE_FXTAP9_SGN XCVR_C10_RX_ADP_VGA_SEL XCVR_C10_RX_EQ_BW_SEL XCVR_C10_RX_EQ_DC_GAIN_TRIM XCVR_C10_RX_LINK XCVR_C10_RX_ONE_STAGE_ENABLE XCVR_C10_RX_TERM_SEL XCVR_C10_TX_COMPENSATION_EN XCVR_C10_TX_LINK XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T XCVR_C10_TX_SLEW_RATE_CTRL XCVR_C10_TX_TERM_SEL XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL XCVR_C10_TX_XTX_PATH_ANALOG_MODE XCVR_RECONFIG_GROUP XCVR_S10_REFCLK_TERM_TRISTATE XCVR_USE_HQ_REFCLK XCVR_USE_SKEW_BALANCED XCVR_VCCR_VCCT_VOLTAGE
Logic Generation Assignments x
IP_BB_LOCATION IP_BB_RELATIVE_LOCATION IP_COLOCATE IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL IP_RECONFIG_GROUP_PARENT IP_RECONFIG_GROUP_SHARED_SIP IP_RECONFIG_ID IP_TILE_ASSIGNMENT IP_TILE_SETTING
Netlist Viewer Assignments x
RTLV_GROUP_COMB_LOGIC_IN_CLOUD RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV RTLV_GROUP_RELATED_NODES RTLV_GROUP_RELATED_NODES_TMV RTLV_REMOVE_FANOUT_FREE_REGISTERS RTLV_SIMPLIFIED_LOGIC
Pin & Location Assignments x
FAST_INPUT_REGISTER FAST_OUTPUT_ENABLE_REGISTER FAST_OUTPUT_REGISTER IP_DEBUG_VISIBLE LOCATION PIN_CONNECT_FROM_NODE RESERVE_PIN SUBCLIQUE_OF VIRTUAL_PIN
Power Estimation Assignments x
EARLY_POWER_ESTIMATOR_EXPORT_FILE ENABLE_SMART_VOLTAGE_ID POWER_ADDITIONAL_MARGIN_PERCENTAGE POWER_AND_THERMAL_CALCULATOR_EXPORT_FILE POWER_APPLY_THERMAL_MARGIN POWER_AUTO_COMPUTE_TJ POWER_BOARD_TEMPERATURE POWER_BOARD_THERMAL_MODEL POWER_COOLING_FOR_MAX_TJ POWER_DEFAULT_INPUT_IO_TOGGLE_RATE POWER_DEFAULT_TOGGLE_RATE POWER_GLITCH_FACTOR POWER_HPS_DYNAMIC_POWER_DUAL POWER_HPS_DYNAMIC_POWER_SINGLE POWER_HPS_ENABLE POWER_HPS_JUNCTION_TEMPERATURE POWER_HPS_PROC_FREQ POWER_HPS_STATIC_POWER POWER_HPS_TOTAL_POWER POWER_HSSI POWER_HSSI_LEFT POWER_HSSI_RIGHT POWER_HSSI_VCCHIP_LEFT POWER_HSSI_VCCHIP_RIGHT POWER_INPUT_FILE_NAME POWER_INPUT_FILE_TYPE POWER_MAX_TJ_VALUE POWER_OCS_VALUE POWER_OJB_VALUE POWER_OJC_VALUE POWER_OSA_VALUE POWER_OUTPUT_SAF_NAME POWER_PRESET_COOLING_SOLUTION POWER_PSI_CA_VALUE POWER_READ_INPUT_FILE POWER_REPORT_POWER_DISSIPATION POWER_REPORT_SIGNAL_ACTIVITY POWER_STATIC_PROBABILITY POWER_TEMPERATURE_MEASUREMENT_METHOD POWER_THERMAL_SOLVER_MODE POWER_TJ_VALUE POWER_TOGGLE_RATE POWER_TOGGLE_RATE_PERCENTAGE POWER_USE_CUSTOM_COOLING_SOLUTION POWER_USE_DEVICE_CHARACTERISTICS POWER_USE_INPUT_FILES POWER_USE_PVA POWER_USE_TA_VALUE POWER_VCCAUX_USER_OPTION POWER_VCCA_GXBL_USER_OPTION POWER_VCCA_GXBR_USER_OPTION POWER_VCCA_GXB_USER_OPTION POWER_VCCA_L_USER_OPTION POWER_VCCA_R_USER_OPTION POWER_VCCCB_USER_OPTION POWER_VCCH_GXBL_USER_OPTION POWER_VCCH_GXBR_USER_OPTION POWER_VCCH_GXB_USER_OPTION POWER_VCCIO_USER_OPTION POWER_VCCL_GXB_USER_OPTION POWER_VCCPD_USER_OPTION POWER_VCCR_GXBL_USER_OPTION POWER_VCCR_GXBR_USER_OPTION POWER_VCCR_GXB_USER_OPTION POWER_VCCT_GXBL_USER_OPTION POWER_VCCT_GXBR_USER_OPTION POWER_VCCT_GXB_USER_OPTION POWER_VCD_FILE_END_TIME POWER_VCD_FILE_START_TIME POWER_VCD_FILTER_GLITCHES VCCAUX_SHARED_USER_VOLTAGE VCCAUX_USER_VOLTAGE VCCA_FPLL_USER_VOLTAGE VCCA_GTBR_USER_VOLTAGE VCCA_GTB_USER_VOLTAGE VCCA_GXBL_USER_VOLTAGE VCCA_GXBR_USER_VOLTAGE VCCA_GXB_USER_VOLTAGE VCCA_L_USER_VOLTAGE VCCA_PLL_USER_VOLTAGE VCCA_R_USER_VOLTAGE VCCA_USER_VOLTAGE VCCBAT_USER_VOLTAGE VCCCB_USER_VOLTAGE VCCD_FPLL_USER_VOLTAGE VCCD_PLL_USER_VOLTAGE VCCD_USER_VOLTAGE VCCEH_GXBL_USER_VOLTAGE VCCEH_GXBR_USER_VOLTAGE VCCEH_GXB_USER_VOLTAGE VCCERAM_USER_VOLTAGE VCCE_GXBL_USER_VOLTAGE VCCE_GXBR_USER_VOLTAGE VCCE_GXB_USER_VOLTAGE VCCE_USER_VOLTAGE VCCHIP_L_USER_VOLTAGE VCCHIP_R_USER_VOLTAGE VCCHIP_USER_VOLTAGE VCCHSSI_L_USER_VOLTAGE VCCHSSI_R_USER_VOLTAGE VCCH_GTBR_USER_VOLTAGE VCCH_GTB_USER_VOLTAGE VCCH_GXBL_USER_VOLTAGE VCCH_GXBR_USER_VOLTAGE VCCH_GXB_USER_VOLTAGE VCCH_L_USER_VOLTAGE VCCH_R_USER_VOLTAGE VCCINT_USER_VOLTAGE VCCIOREF_HPS_USER_VOLTAGE VCCIO_HPS_USER_VOLTAGE VCCIO_USER_VOLTAGE VCCL_GTBL_USER_VOLTAGE VCCL_GTBR_USER_VOLTAGE VCCL_GTB_USER_VOLTAGE VCCL_GXBL_USER_VOLTAGE VCCL_GXBR_USER_VOLTAGE VCCL_GXB_USER_VOLTAGE VCCL_HPS_USER_VOLTAGE VCCL_USER_VOLTAGE VCCPD_USER_VOLTAGE VCCPGM_USER_VOLTAGE VCCPLL_HPS_USER_VOLTAGE VCCPT_USER_VOLTAGE VCCP_USER_VOLTAGE VCCRSTCLK_HPS_USER_VOLTAGE VCCR_GTBL_USER_VOLTAGE VCCR_GTBR_USER_VOLTAGE VCCR_GTB_USER_VOLTAGE VCCR_GXBL_USER_VOLTAGE VCCR_GXBR_USER_VOLTAGE VCCR_GXB_USER_VOLTAGE VCCR_L_USER_VOLTAGE VCCR_R_USER_VOLTAGE VCCR_USER_VOLTAGE VCCT_GTBL_USER_VOLTAGE VCCT_GTBR_USER_VOLTAGE VCCT_GTB_USER_VOLTAGE VCCT_GXBL_USER_VOLTAGE VCCT_GXBR_USER_VOLTAGE VCCT_GXB_USER_VOLTAGE VCCT_L_USER_VOLTAGE VCCT_R_USER_VOLTAGE VCCT_USER_VOLTAGE VCC_HPS_USER_VOLTAGE VCC_USER_VOLTAGE
Programmer Assignments x
GENERATE_CONFIG_HEXOUT_FILE GENERATE_CONFIG_ISC_FILE GENERATE_CONFIG_JAM_FILE GENERATE_CONFIG_JBC_FILE GENERATE_CONFIG_JBC_FILE_COMPRESSED GENERATE_CONFIG_SVF_FILE GENERATE_JAM_FILE GENERATE_JBC_FILE GENERATE_JBC_FILE_COMPRESSED GENERATE_SVF_FILE HPS_EARLY_IO_RELEASE MERGE_HEX_FILE
Project-Wide Assignments x
AHDL_FILE AHDL_TEXT_DESIGN_OUTPUT_FILE ALLOW_DSP_RETIMING ALLOW_RAM_RETIMING ASM_FILE AUTO_EXPORT_VER_COMPATIBLE_DB BASE_REVISION_PROJECT_OUTPUT_DIRECTORY BDF_FILE BINARY_FILE BSF_FILE CDC_MISC_FILE CDC_SYSTEMVERILOG_FILE CDC_VERILOG_FILE CDF_FILE COMMAND_MACRO_FILE CPP_FILE CPP_INCLUDE_FILE CUSP_FILE C_FILE DEPENDENCY_FILE DESIGN_ASSISTANT_INCLUDE_IP_BLOCKS DESIGN_ASSISTANT_MAX_VIOLATIONS_PER_RULE DESIGN_ASSISTANT_WAIVER_FILE DRC_RAM_INFERENCE_HIGH_FANOUT_NET_THRESHOLD DSPBUILDER_FILE EDIF_FILE ELF_FILE ENABLE_COMPACT_REPORT_TABLE ENABLE_FIT_RPT_RESOURCE_BY_ENTITY ENABLE_REDUCED_MEMORY_MODE EQUATION_FILE ERROR_ON_INVALID_ENTITY_NAME EXPORT_PARTITION_SNAPSHOT_FINAL EXPORT_PARTITION_SNAPSHOT_SYNTHESIZED FLOW_DISABLE_ASSEMBLER FLOW_ENABLE_DESIGN_ASSISTANT FLOW_ENABLE_EDA_NETLIST_WRITER FLOW_ENABLE_INTERACTIVE_TIMING_ANALYZER FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS FLOW_ENABLE_PARALLEL_MODULES FLOW_ENABLE_POWER_ANALYZER FLOW_ENABLE_RTL_VIEWER GDF_FILE HEX_FILE HEX_OUTPUT_FILE HPS_ISW_DATA HPS_ISW_EMIF HPS_ISW_FILE HTML_FILE HTML_REPORT_FILE INCLUDE_FILE INVALID_DESIGN_SOURCE IPX_FILE IP_COMPONENT_AUTHOR IP_COMPONENT_DESCRIPTION IP_COMPONENT_DISPLAY_NAME IP_COMPONENT_DOCUMENTATION_LINK IP_COMPONENT_GROUP IP_COMPONENT_INTERNAL IP_COMPONENT_NAME IP_COMPONENT_PARAMETER IP_COMPONENT_REPORT_HIERARCHY IP_COMPONENT_VERSION IP_FILE IP_GENERATED_DEVICE_FAMILY IP_QSYS_MODE IP_TARGETED_DEVICE_FAMILY IP_TARGETED_PART_TRAIT IP_TOOL_ENV IP_TOOL_HIERARCHY_LEVELS IP_TOOL_NAME IP_TOOL_VENDOR_NAME IP_TOOL_VERSION IP_TOOL_VERSION_CREATED IP_TOP_LEVEL_COMPONENT_NAME IP_TOP_LEVEL_ENTITY_NAME JAM_FILE JBC_FILE LICENSE_FILE LMF_FILE LOGIC_ANALYZER_INTERFACE_FILE MAP_FILE MAX_IGNORED_ASGN_MSG MESSAGE_DISABLE MESSAGE_ENABLE MIF_FILE MISC_FILE NUM_PARALLEL_PROCESSORS OBJECT_FILE OCP_FILE PARTIAL_SRAM_OBJECT_FILE PIN_FILE POWER_INPUT_FILE PPF_FILE PROGRAMMER_OBJECT_FILE PROJECT_OUTPUT_DIRECTORY PROJECT_USE_SIMPLIFIED_NAMES PROMOTE_WARNING_TO_ERROR QARLOG_FILE QAR_FILE QIP_FILE QSYS_FILE QUARTUS_PTF_FILE QUARTUS_SBD_FILE QUARTUS_STANDARD_DELAY_FILE RAW_BINARY_FILE READ_OR_WRITE_IN_BYTE_ADDRESS REVISION_TYPE RUN_FULL_COMPILE_ON_DEVICE_CHANGE SBI_FILE SDC_ENTITY_FILE SDC_ENTITY_HELPER_FILE SDC_FILE SDF_OUTPUT_FILE SERIAL_BITSTREAM_FILE SIGNALTAP_FILE SIP_FILE SLD_FILE SMF_FILE SOFTWARE_LIBRARY_FILE SOPCINFO_FILE SOPC_FILE SOURCE_TCL_SCRIPT_FILE SPD_FILE SPYGLASS_MISC_FILE SPYGLASS_SYSTEMVERILOG_FILE SPYGLASS_VERILOG_FILE SRAM_OBJECT_FILE SRECORDS_FILE SVF_FILE SYM_FILE SYNTHESIS_ONLY_QIP SYSTEMVERILOG_FILE TCL_ENTITY_FILE TCL_SCRIPT_FILE TEMPLATE_FILE TEXT_FILE TEXT_FORMAT_REPORT_FILE TIMING_ANALYSIS_OUTPUT_FILE USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT VCD_FILE VECTOR_TABLE_OUTPUT_FILE VECTOR_TEXT_FILE VECTOR_WAVEFORM_FILE VERILOG_FILE VERILOG_INCLUDE_FILE VERILOG_OUTPUT_FILE VERILOG_TEST_BENCH_FILE VER_COMPATIBLE_DB_DIR VHDL_FILE VHDL_OUTPUT_FILE VHDL_TEST_BENCH_FILE VQM_FILE ZIP_VECTOR_WAVEFORM_FILE
Retimer Assignments x
HYPER_RETIMER_ADD_PIPELINING HYPER_RETIMER_ADD_PIPELINING_GROUP HYPER_RETIMER_ENABLE_ADD_PIPELINING HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION
Retimer Fast Forward Assignments x
CRITICAL_CHAIN_VIEWER FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD HYPER_RETIMER_FAST_FORWARD_CUT_ALL_CLOCK_TRANSFERS HYPER_RETIMER_FAST_FORWARD_ON_HIERARCHY
Signal Probe Assignments x
CONNECT_SIGNALPROBE_PIN CREATE_SIGNALPROBE_PIN
Signal Tap Assignments x
CREATE_PARTITION_BOUNDARY_PORTS ENABLE_LOGIC_ANALYZER_INTERFACE ENABLE_SIGNALTAP PRESERVE_FOR_DEBUG PRESERVE_FOR_DEBUG_ENABLE STP_FILE USE_LOGIC_ANALYZER_INTERFACE_FILE USE_SIGNALTAP_FILE
Simulator Assignments x
ACTION ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS ADD_TO_SIMULATION_OUTPUT_WAVEFORMS ALIAS AUTO_USE_SIMULATION_PDB_NETLIST BREAKPOINT_STATE CHECK_OUTPUTS END_TIME EXTERNAL_PIN_CONNECTION GLITCH_DETECTION GLITCH_INTERVAL IMMEDIATE_ASSERTION_FAIL_ACTION IMMEDIATE_ASSERTION_FAIL_MESSAGE IMMEDIATE_ASSERTION_PASS_MESSAGE IMMEDIATE_ASSERTION_STATE IMMEDIATE_ASSERTION_TEST_CONDITION INCREMENTAL_VECTOR_INPUT_SOURCE PASSIVE_RESISTOR SETUP_HOLD_DETECTION SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED SETUP_HOLD_TIME_VIOLATION_DETECTION SIMULATION_BUS_CHANNEL_GROUPING SIMULATION_COMPARE_SIGNAL SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL SIMULATION_COVERAGE SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL SIMULATION_MODE SIMULATION_NETLIST_VIEWER SIMULATION_SIGNAL_COMPARE_TOLERANCE SIMULATION_VDB_RESULT_FLUSH SIMULATION_VECTOR_COMPARE_BEGIN_TIME SIMULATION_VECTOR_COMPARE_END_TIME SIMULATION_VECTOR_COMPARE_RULE_FOR_0 SIMULATION_VECTOR_COMPARE_RULE_FOR_1 SIMULATION_VECTOR_COMPARE_RULE_FOR_DC SIMULATION_VECTOR_COMPARE_RULE_FOR_H SIMULATION_VECTOR_COMPARE_RULE_FOR_L SIMULATION_VECTOR_COMPARE_RULE_FOR_U SIMULATION_VECTOR_COMPARE_RULE_FOR_W SIMULATION_VECTOR_COMPARE_RULE_FOR_X SIMULATION_VECTOR_COMPARE_RULE_FOR_Z SIM_BEHAVIOR_SIMULATION SIM_COMPILE_HDL_FILES SIM_HDL_TOP_MODULE_NAME SIM_OVERWRITE_WAVEFORM_INPUTS SIM_TAP_REGISTER_D_Q_PORTS SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE SIM_VECTOR_COMPARED_CLOCK_OFFSET SIM_VECTOR_COMPARED_CLOCK_PERIOD START_TIME TRIGGER_EQUATION TRIGGER_VECTOR_COMPARE_ON_SIGNAL USER_MESSAGE VECTOR_COMPARE_TRIGGER_MODE VECTOR_INPUT_SOURCE VECTOR_OUTPUT_DESTINATION VECTOR_OUTPUT_FORMAT X_ON_VIOLATION_OPTION
Intel® Quartus® Prime Pro Edition Settings File Reference Manual

CLOCK_REGION

Specifies the placement of the clock region of a global signal for floorplanning reasons. For example, a Clock Region assignment can be used to ensure that a certain area of the device has access to a global signal, throughout all future design iterations. A Clock Region assignment can also be used in cases of congestion involving global signal resources. By specifying a smaller clock region size, the assignment prevents a signal using spine clock and other clock routing resources in the excluded sectors that may be encountering clock-related congestion.\n\nFor devices up to and including Arria 10, this assignment takes as its value the names of those Global, Regional, Periphery or Spine Clock regions. These region names are visible in Chip Planner by enabling the appropriate Clock Region layer in the Layers Settings dialog box. Examples of valid values include \"Regional Clock Region 1\" or \"Periphery Clock Region 1\". When constraining a global signal to a smaller than normal region, for example, to avoid clock congestion, you may specify a clock region of a different type than the global resources being used. For example, a signal with a Global Signal assignment of \"Global Clock\", but a Clock Region assignment of \"Regional Clock Region 0\", constrains the clock to use global network routing resources, but only to the region covered by Regional Clock Region 0. To provide a finer level of control, you can also list multiple smaller clock regions, separated by commas. For example: \"Periphery Clock Region 0, Periphery Clock Region 1\" constrains a signal to only the area reachable by those two periphery clock networks.\n\nFor Stratix 10 devices, clock regions can be constrained to a rectangle whose dimensions are defined by the sector grid, as seen in the Clock Sector Region layer of the Chip Planner. This assignment specifies the bottom left and top right coordinates of the rectangle in the format \"SX# SY# SX# SY#\". For example, \"SX0 SY0 SX1 SY1\" constrains the clock to a 2x2 region, from the bottom left of sector (0,0) to the top right of sector (1,1). For a constraint spanning only one sector, it is sufficient to specify the location of that sector, for example \"SX1 SY1\". The bounding rectangle can also be specified by the bottom left and top right corners in chip coordinates, for example, \"X37 Y181 X273 Y324\". However, such a constraint should be sector aligned (using sector coordinates guarantees this) or the Fitter automatically snaps to the smallest sector aligned rectangle that still encompasses the original assignment. The \"SX# SY# SX# SY#\"|\"X# Y# X# Y#\" strings are case-insensitive.

Type

String

Device Support

  • Intel® Agilex™
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Intel® Stratix® 10

Notes

This assignment supports wildcards.

This assignment supports Fitter wildcards.

Syntax


set_instance_assignment -name CLOCK_REGION -to <to> -entity <entity name> <value>
set_instance_assignment -name CLOCK_REGION -from <from> -to <to> -entity <entity name> <value>
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