AN 881: PCI Express* Gen3 x16 Avalon® Memory Mapped (Avalon-MM) DMA with DDR4 SDRAM and HBM2 Memories Reference Design

Download PDF
ID 683291
Date 4/19/2021
Public

Visible to Intel only — GUID: ueg1560381064865

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
1. Introduction 2. Reference Design Description 3. Understanding PCI Express* throughput 4. Document Revision History for AN 881: PCI Express* Gen3 x16 Avalon® Memory Mapped (Avalon-MM) DMA with External and HBM2 Memories Reference Design
1. Introduction x
1.1. PCI Express Gen3 x16 Avalon-MM DMA with External and HBM2 Memory Hardware and Software Requirements 1.2. Avalon-MM Bridge with DMA Module Description 1.3. DMA Procedure Steps 1.4. Setting Up the Hardware 1.5. Installing the DMA Test Driver and Running the Linux DMA Software
2. Reference Design Description x
2.1. Project Hierarchy 2.2. Parameter Settings for PCI Express* Hard IP Variations 2.3. PCIe Avalon-MM DMA Reference Design with External and HBM2 Memories Platform Designer System 2.4. Intel Stratix 10 MX DMA Memory Throughput
3. Understanding PCI Express* throughput x
3.1. Throughput for Posted Writes 3.2. Throughput for Reads
3.1. Throughput for Posted Writes x
3.1.1. Specifying the Maximum Payload Size
3.2. Throughput for Reads x
3.2.1. Understanding Throughput Measurement
1. Introduction
2. Reference Design Description
3. Understanding PCI Express* throughput
4. Document Revision History for AN 881: PCI Express* Gen3 x16 Avalon® Memory Mapped (Avalon-MM) DMA with External and HBM2 Memories Reference Design

2.4. Intel Stratix 10 MX DMA Memory Throughput

Figure 8. Intel Stratix 10 MX DMA Memory Throughput with DDR4 Memory
Figure 9. Intel Stratix 10 MX DMA Memory Throughput with HBM2 Memory
Level Two Title