F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

Download PDF
ID 683287
Date 10/14/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode PAM4 with RS-FEC Enabled in Full Transfer Mode Simulation Result NRZ without RS-FEC Enabled in Full Transfer Mode Simulation Result
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.3.2. Simulation Result for Full Mode

In full mode or packet transfer mode, the traffic generator generates 10,000 words in a random number of bursts and transmits to the IP once the TX and RX links are established. The words are looped back to the RX MAC. The RX MAC then sends the burst to the traffic checker for data verification. In the simulation results, you can find the following information:
  • TX and RX link status
  • Configuration settings of the IP
  • Number of sample words sent per burst
  • Test results with the total number of words transferred, number of bursts, and link latency value

The following are samples of simulation results for each design example variant.

PAM4 with RS-FEC Enabled in Full Transfer Mode Simulation Result

Note: NRZ with RS-FEC enabled variant has similar simulation result as PAM4 with RS-FEC enabled variant. 
#    Waiting for TX Link Up
# 
#    Phy TX Lanes Stable asserted at time 354081776
# 
#    Phy EHIP ready asserted at time 475222181
# 
#    TX link_up asserted at time 475228320
#       TX user_clock frequency              = 3.731343e+02 MHz
#       RX user_clock frequency              = 3.731343e+02 MHz
#    
#    *************************************** Test Started *************************************
#    
#    Tests started at time 475239040
#    
#    LANES                         = 4
#    
#    Streaming Mode                = FULL
#    
#    SRL4 Align Period             = 128
#    
#    RSFEC Enable                  = 1
#    
#    PER LANE CRC ENABLE Enable    = 0
#    
#    ******************************* Data Forwarding Test Initialize *****************************
#    
#    Waiting for RX Link Up
# 
#    Phy block lock asserted at time 495699771
# 
#    Phy RX PCS Ready asserted at time 495731094
# 
#    RX link_up asserted at time 495786600
#    
#    ******************************* Data Forwarding Test Started *****************************
#    
#    Test Mode:            Burst
#    User Stall Insertion: Disabled
#    
# 
#    Traffic Generator: 98 sample burst started at time 495797320
# 
#    Traffic Generator: 17 sample burst started at time 496110880
.
.
.
#    Traffic Checker: Burst start descriptor read at time 534212440
#                     Sync value 242
#                     Sample number 9907
# 
#    Traffic Checker: Burst end descriptor read at time 534534040
#                     Inter-burst interval 7
#                     Empty value 0
#                     Sample number 10000
#    
#    ****************************** Data Forwarding Test Completed ****************************
#    
#    ************************************** Test Completed ************************************
#    
#    End time                       = 534810080
#    
#    Total words tranferred         = 10000
#    
#    Number of bursts               = 196
#    
#    Random number generator seed   = 1756255697
#    
#    Link Latency                   = 0 ns
#    
#    *************************************** Test Passed **************************************

NRZ without RS-FEC Enabled in Full Transfer Mode Simulation Result 

#    Waiting for TX Link Up
# 
#    Phy TX Lanes Stable asserted at time 3007624010
# 
#    Phy EHIP ready asserted at time 4397012810
# 
#    TX link_up asserted at time 4397112640
#       TX user_clock frequency              = 3.511236e+02 MHz
#       RX user_clock frequency              = 3.511236e+02 MHz
#    
#    *************************************** Test Started *************************************
#    
#    Tests started at time 4397226560
#    
#    LANES                         = 2
#    
#    Streaming Mode                = FULL
#    
#    SRL4 Align Period             = 128
#    
#    RSFEC Enable                  = 0
#    
#    PER LANE CRC ENABLE Enable    = 0
#    
#    ******************************* Data Forwarding Test Initialize *****************************
#    
#    Waiting for RX Link Up
# 
#    Phy block lock asserted at time 4423739210
# 
#    Phy RX PCS Ready asserted at time 4424123210
# 
#    RX link_up asserted at time 4425564160
#    
#    ******************************* Data Forwarding Test Started *****************************
#    
#    Test Mode:            Continuous
#    User Stall Insertion: Disabled
#    
# 
#    Traffic Generator: 10000 sample continuous transfer started at time 4425678080
# 
#    Traffic Checker: Burst start descriptor read at time 4428412160
#                     Sync value 125
#                     Sample number 1
# 
#    Traffic Checker: Burst end descriptor read at time 4811468160
#                     Inter-burst interval 0
#                     Empty value 0
#                     Sample number 10000
#    
#    ****************************** Data Forwarding Test Completed ****************************
#    
#    ************************************** Test Completed ************************************
#    
#    End time                       = 4814401600
#    
#    Total words tranferred         = 10000
#    
#    Number of bursts               = 1
#    
#    Random number generator seed   = 1221861777
#    
#    Link Latency                   = 2900 ns
#    
#    *************************************** Test Passed **************************************
Level Two Title