F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

Download PDF
ID 683287
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software and Hardware Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.7.1. Setting Up and Running the Toolkit

To enable the F-Tile Serial Lite IV IP toolkit, you must download and run the toolkit.
To run the toolkit, follow these steps:
  1. Generate the design example after you specify the parameters.
  2. Compile the design example to generate a .sof file.
  3. In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
  4. In the system console, click Load Design and select the .sof file for the design example.
  5. Under the list of Instances, select sliv_ip_toolkit_1.0.
  6. Under the Details pane, select F-Tile Serial Lite IV IP Toolkit and click Open Toolkit to launch the toolkit.
    Figure 13. Launch the F-Tile Serial Lite IV IP Toolkit
When the toolkit is up and running, set JTAG master by following the instructions given in the display window.
Figure 14. Setting JTAG Master
Related Information
Level Two Title