F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software and Hardware Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 3.0.0

This document provides features, usage guidelines, and functional description of the F-Tile Serial Lite IV Intel® FPGA IP design examples using F-tile transceivers in Intel® Agilex® devices.

Intended Audience

This document is intended for the following users:
  • Design architects to make IP selection during system level design planning phase.
  • Hardware designers when integrating the IP into their system level design.
  • Validation engineers during system level simulation and hardware validation phase.

Acronyms and Glossary

Table 1.  Acronym List
Acronym Expansion
CW Control Word
RS-FEC Reed-Solomon Forward Error Correction
PMA Physical Medium Attachment
TX Transmitter
RX Receiver
PAM4 Pulse-Amplitude Modulation 4-Level
NRZ Non-return-to-zero
PCS Physical Coding Sublayer
MII Media Independent Interface
XGMII 10 Gigabit Media Independent Interface
Level Two Title