F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 10/22/2021
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Error Handling 3.5. Link Debugging Sequence 3.6. F-Tile Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.6. F-Tile Serial Lite IV IP Toolkit x
3.6.1. Setting Up and Running the Toolkit 3.6.2. Toolkit GUI Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.1. Features

You can use the design example to test the following features of the F-Tile Serial Lite IV Intel® FPGA IP:
  • Basic and full transmission modes:
    • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
    • Full mode—This is a packet transfer mode. This mode sends a burst and a sync cycle at the start and end of a packet as delimiters.
  • Transceiver data rate:
    • For PAM4 mode 1:
      • FHT supports only 56.1 Gbps per lane with a maximum of 4 lanes.
      • FGT supports up to 58 Gbps per lane with a maximum of 12 lanes.
    • For NRZ mode 1:
      • FHT supports only 28.05 Gbps per lane with a maximum of 4 lanes.
      • FGT is supporting up to 28.05 Gbps per lane with a maximum of 16 lanes.
  • Data error reporting including PCS errors, loss of alignment, CRC errors, and data invalid errors on the RX datapath.
  • Traffic checker for data verification and lane deskew verification.
1 The maximum data rate that the IP can achieve depends on the device speed grade. Refer to Intel® Agilex® Device Data Sheet for more information about maximum data rate for each device speed grade.
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