F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 10/22/2021
Public

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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Error Handling 3.5. Link Debugging Sequence 3.6. F-Tile Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.6. F-Tile Serial Lite IV IP Toolkit x
3.6.1. Setting Up and Running the Toolkit 3.6.2. Toolkit GUI Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

2.5. Compiling and Testing the Design

Follow these steps to compile and test the design:

  1. Launch the Intel® Quartus® Prime Pro Edition software and change the directory to example_design_dir/ed_synth/ and open the seriallite_iv_streaming_demo.qpf file.
  2. Click Processing> Start Compilation to compile the design.

    The Intel® Quartus® Prime Pro Edition software automatically loads the timing constraints for the design example and the design components during compilation.

The design includes a Synopsys Design Constraints File (.sdc) and an Intel® Quartus® Prime Pro Edition Settings File (.qsf) with verified constraints in loopback mode. If you use the design example with another device or development board, you may need to update the device settings and constraints in the .qsf file.

Level Two Title