Visible to Intel only — GUID: mlz1632799091356
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: mlz1632799091356
Ixiasoft
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
If an IP core version is not listed, the user guide for the previous IP core version applies.
Intel® Quartus® Prime Version | IP Core Version | User Guide |
---|---|---|
21.3 | 3.0.0 | F-Tile CPRI PHY Intel FPGA IP User Guide |
21.2 | 2.0.0 | F-Tile CPRI PHY Intel FPGA IP User Guide |