F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Features 2.2. Simulation Design Example 2.3. Hardware Design Example 2.4. Interface Signals 2.5. Design Example Registers
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

2.3. Hardware Design Example

Figure 5. Hardware Design Example Block Diagram
The F-Tile CPRI PHY Intel® FPGA IP core hardware design example includes the following components:
  • F-Tile CPRI PHY Intel® FPGA IP core.
  • Packet client logic block that generates and receives traffic.
  • Round trip counter.
  • IOPLL to generate sampling clock for deterministic latency logic inside the IP, and round trip counter component at testbench.
  • System PLL to generate system clocks for the IP.
  • Avalon® -MM address decoder to decode reconfiguration address space for CPRI, Transceiver, and Ethernet modules during reconfiguration accesses.
  • Sources and probes for asserting resets and monitoring the clocks and a few status bits.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through System Console.
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