F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 10/04/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Features 2.2. Simulation Design Example 2.3. Hardware Design Example 2.4. Interface Signals 2.5. Design Example Registers
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

2.5. Design Example Registers

Table 6.  Design Example Registers
Channel Number Base Address (Byte Address) Register Type
0 0x00000000 CPRI PHY Reconfiguration registers for Channel 0
0x00100000 Ethernet Reconfiguration registers for Channel 0
0x00200000 Transceiver Reconfiguration registers for Channel 0
1 2 0x01000000 CPRI PHY Reconfiguration registers for Channel 1
0x01100000 Ethernet Reconfiguration registers for Channel 1
0x01200000 Transceiver Reconfiguration registers for Channel 1
22 0x02000000 CPRI PHY Reconfiguration registers for Channel 2
0x02100000 Ethernet Reconfiguration registers for Channel 2
0x02200000 Transceiver Reconfiguration registers for Channel 2
32 0x03000000 CPRI PHY Reconfiguration registers for Channel 3
0x03100000 Ethernet Reconfiguration registers for Channel 3
0x03200000 Transceiver Reconfiguration registers for Channel 3
2 These registers are reserved if the channel is not used.
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