Intel® FPGA Programmable Acceleration Card N3000 Data Sheet

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ID 683260
Date 6/30/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. Intel® Provided FPGA Image A. References B. Safety and Regulatory Information C. Document Revision History for Intel® FPGA Programmable Acceleration Card N3000 Data Sheet
2. Overview x
2.1. Intel® FPGA PAC N3000 Block Diagram 2.2. Overview of Product Features 2.3. PCIe Overview 2.4. Board Management Controller Overview
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GT FPGA 2.2.2. Intel® Ethernet Controller XL710-BM2 Network Interface Controller 2.2.3. On-Board Memory 2.2.4. Software and Firmware 2.2.5. Power 2.2.6. Network Interface
2.2.6. Network Interface x
2.2.6.1. Intel® Ethernet Connection C827 Retimer
2.4. Board Management Controller Overview x
BMC Features Sensor Monitoring Features 2.4.1. Field Replaceable Unit Identification (FRUID) EEPROM
5. Thermal Specifications x
5.1. Cooling Requirements
B. Safety and Regulatory Information x
B.1. Regulatory Compliance
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. Intel® Provided FPGA Image
A. References
B. Safety and Regulatory Information
C. Document Revision History for Intel® FPGA Programmable Acceleration Card N3000 Data Sheet

2.4. Board Management Controller Overview

The Intel® FPGA PAC N3000 contains an Intel® MAX® 10 Board Management Controller (BMC). This BMC is responsible for controlling, monitoring and giving low-level access to board features. The Intel® MAX® 10 BMC interfaces with on-board sensors, the FPGA and the flash, and controls power-on/power-off sequences, FPGA configuration and telemetry data polling. The BMC communicates with the server system controller using either Platform Level Data Model (PLDM) version 1.1.1 protocol or I2C via the PCIe* SMBus.

An external Quad SPI flash stores the BMC firmware and the BMC firmware for the Nios II is field upgradeable over the PCIe* using the remote system update feature. Only Intel provided BMC firmware is permitted.

BMC Features

  • Supports FPGA configuration and reconfiguration.
  • Supports Secure Remote System Update for Intel® MAX® 10 BMC FPGA update image, Intel® Arria® 10 GT FPGA user image, and Nios® firmware image.
  • Monitors telemetry data for board temperature, voltage, and current.
  • Reports telemetry data to host BMC via Platform Level Data Model (PLDM) over Management Component Transport Protocol (MCTP) SMBus.
  • Provides protective action when temperature and auxiliary power readings are outside of critical thresholds.
  • Provides power up/down sequencing and fault detection with automatic shut-down protection.
  • Interfaces with sensors, FPGA, flash, and QSFPs.

Sensor Monitoring Features

The Intel® FPGA PAC N3000 incorporates sensor monitoring that allow the host server to read telemetry data such as voltage, current, power, and temperature information from various components on the board. The host system controller accesses these sensors using either PLDM over MCTP or I2C via the PCIe* SMBus.
Table 5.  Platform Descriptor Records (PDR) Sensor Names and Record Handles
Sensor Name PLDM
PDR Record Handle Thresholds in PDR Supports Threshold changes via PLDM
Board Power 1 0 NO
12 V Backplane Current 2 0 NO
12 V Backplane Voltage 3 0 NO
1.2 V Voltage 4 0 NO
1.8 V Voltage 6 0 NO
3.3 V Voltage 8 0 NO
FPGA Core Voltage 10 0 NO
FPGA Core Current 11 0 NO
FPGA Core Temperature 12 Upper Warning: 90 Upper Fatal: 100 YES
Board Temperature 13 Upper Warning: 75 Upper Fatal: 85 YES
QSFP0 Voltage 14 0 NO
QSFP0 Temperature 15 Upper Warning: 80 Upper Fatal: 90 YES
12 V AUX Current 24 0 NO
12 V AUX Voltage 25 0 NO
QSFP1 Voltage 37 0 NO
QSFP1 Temperature 38 Upper Warning: 80 Upper Fatal: 90 YES
PKVL A Core Temperature 44 0 NO
PKVL A Serdes Temperature 45 0 NO
PKVL B Core Temperature 46 0 NO
PKVL B Serdes Temperature 47 0 NO

Refer to Board Monitoring through I2C SMBus section of the Intel FPGA PAC N3000 BMC User Guide for information on telemetry data register map.

The BMC shuts down power to the board under the following conditions:
  • 12 V Auxiliary or 12 V backplane supply voltage is below 10.46 V
  • FPGA core temperature reaches 100 °C
  • Board temperature reaches 85 °C

Section Content
Field Replaceable Unit Identification (FRUID) EEPROM

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