Intel® FPGA Programmable Acceleration Card N3000 Data Sheet

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ID 683260
Date 6/30/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. Intel® Provided FPGA Image A. References B. Safety and Regulatory Information C. Document Revision History for Intel® FPGA Programmable Acceleration Card N3000 Data Sheet
2. Overview x
2.1. Intel® FPGA PAC N3000 Block Diagram 2.2. Overview of Product Features 2.3. PCIe Overview 2.4. Board Management Controller Overview
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GT FPGA 2.2.2. Intel® Ethernet Controller XL710-BM2 Network Interface Controller 2.2.3. On-Board Memory 2.2.4. Software and Firmware 2.2.5. Power 2.2.6. Network Interface
2.2.6. Network Interface x
2.2.6.1. Intel® Ethernet Connection C827 Retimer
2.4. Board Management Controller Overview x
2.4.1. Field Replaceable Unit Identification (FRUID) EEPROM
5. Thermal Specifications x
5.1. Cooling Requirements
B. Safety and Regulatory Information x
B.1. Regulatory Compliance
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. Intel® Provided FPGA Image
A. References
B. Safety and Regulatory Information
C. Document Revision History for Intel® FPGA Programmable Acceleration Card N3000 Data Sheet

6. Intel® Provided FPGA Image

The Intel® Arria® 10 FPGA factory image includes the following Intellectual Property (IP) to support in the development of function accelerators:
  • The PCIe IP core
  • The Core Cache Interface protocol (CCI-P) fabric
  • DDR4 memory interface controller IP
  • QDR4 memory interface controller IP
  • 10 or 25 GbE physical interface and MACs with pass-through connectivity between Intel® Ethernet Connection C827 Retimer and Intel® Ethernet Controller XL710-BM2
  • FPGA Management Engine (FME)
  • Nios® core to configure the Intel Ethernet Connection C827 Retimers
Specific features of the factory image are listed in the following document:
  • Intel Acceleration Stack User Guide for Intel® FPGA Programmable Acceleration Card N3000.

The 1024 Mb FPGA flash memory stores two FPGA images. One image is the user image and the other image is a backup factory image. The factory image is only loaded when the user image fails to load from flash to the FPGA.

The Intel® FPGA PAC N3000 does not support partial reconfiguration. The FPGA image is a full-device bit stream that is loaded when the system is powered up or after you enter a remote system update command.

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