• Removed information about Intel® HLS Compiler Pro Edition.

  For best practices information for the Intel® HLS Compiler Pro Edition, see Intel® HLS Compiler Pro Edition Best Practices Guide.

• Added Control LSUs For Your Variable-Latency MM Master Interfaces.
• Updated Memory Architecture Best Practices to list updated and improved tutorials and new memory attributes.
• Split memory architecture examples for overriding coalesced memory architectures and overriding banked memory architectures into the following sections:
  • Example: Overriding a Coalesced Memory Architecture
  • Example: Overriding a Coalesced Memory Architecture
  • Example: Specifying Bank-Selection Bits for Local Memory Addresses
  • Example: Specifying Bank-Selection Bits for Local Memory Addresses

• Maintenance release.

• Added new chapter to cover best practices when using HLS tasks in System of Tasks.
• Moved some content from Loop Best Practices into a new section called Reuse Hardware By Calling It In a Loop.
• Revised Component Gets Bad Quality of Results to include information about the hls_scheduler_target_fmax_mhz component attribute.

• Updated to Loop Best Practices to include information about function inlining in components and using loops to minimize the resulting hardware duplication.

• The Intel® HLS Compiler has a new front end. For a summary of the changes introduced by this new front end, see Improved Intel HLS Compiler Front End in the Intel® High Level Synthesis Compiler Version 18.1 Release Notes.
• The --promote-integers flag and the best_practices/integer_promotion tutorial are no longer supported in Pro Edition because integer promotion is now done by default. References to these items were adjusted to indicate that they apply to Standard Edition only in the following topics:
  • Component Fails Only in Cosimulation
  • Datatype Best Practices

• Added a new chapter, Advanced Troubleshooting, to help you troubleshoot when your component behaves differently in cosimulation and emulation, and when your component has unexpectedly poor performance, resource utilization, or both.

• Starting with Intel® Quartus® Prime Version 18.0, the features and devices supported by the Intel® HLS Compiler depend on what edition of Intel® Quartus® Prime you have. Intel® HLS Compiler publications now use icons to indicate content and features that apply only to a specific edition as follows:

  Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Pro Edition.

  Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Standard Edition.

• Added best_practices/loop_coalesce to the list of tutorials in Loop Best Practices.
• Added interfaces/explicit_streams_packets_ready_empty to list of tutorials in Interface Best Practices.
• Revised Example: Specifying Bank-Selection Bits for Local Memory Addresses with improved descriptions and new graphics that reflect what you would see in the high-level design reports (report.html) for the example component.
• Updated Example: Overriding a Coalesced Memory Architecture with new images to show the memory structures as well as how the FPGA resource usage differs between the two components

• Added Choose the Right Interface for Your Component section to show how changing your component interface affects your component QoR even when the algorithm stays the same.
• Added interface overview tutorial to the list of tutorials in Interface Best Practices.

Parts of this book consist of content previously found in the Intel® High Level Synthesis Compiler User Guide and the Intel® High Level Synthesis Compiler Reference Manual.