Visible to Intel only — GUID: mwh1410383695054
Ixiasoft
Visible to Intel only — GUID: mwh1410383695054
Ixiasoft
2.4.1.2. Creating Virtual Clocks
To create virtual clocks, use the create_clock constraint with no value for the <targets> option.
This following example defines a 100 MHz virtual clock because the command includes no <targets>.
create_clock -period 10 -name my_virt_clk
I/O Constraints with Virtual Clocks
You can use a base clock to constrain the circuit in the FPGA and a virtual clock to represent the clock driving the external device. .
The following example creates the 10 ns virt_clk virtual clock, with a 50% duty cycle, with the first rising edge occurring at 0 ns. The virtual clock can then become the clock source for an output delay constraint.
Virtual Clock Constraints
#create base clock for the design create_clock -period 5 [get_ports system_clk] #create the virtual clock for the external register create_clock -period 10 -name virt_clk #set the output delay referencing the virtual clock set_output_delay -clock virt_clk -max 1.5 [get_ports dataout] set_output_delay -clock virt_clk -min 0.0 [get_ports dataout]
You can verify correct implementation of clock constraints by using Report Clocks (report_clocks) to generate clock timing reports. You can use Check Timing (check_timing) to report problems with a variety of timing constraints, such as the number of unreferenced virtual clocks without constraint.