Visible to Intel only — GUID: mwh1417734823782
Ixiasoft
Visible to Intel only — GUID: mwh1417734823782
Ixiasoft
2.4.1.2.2. I/O Interface Clock Uncertainty Example
When the set_input_delay or set_output_delay commands reference a clock port or PLL output, the virtual clock allows the derive_clock_uncertainty command to apply separate clock uncertainties for internal clock transfers and I/O interface clock transfers.
Create the virtual clock with the same properties as the original clock that is driving the I/O port, as the following example shows:
SDC Commands to Constrain the I/O Interface
# Create the base clock for the clock port create_clock -period 10 -name clk_in [get_ports clk_in] # Create a virtual clock with the same properties of the base clock # driving the source register create_clock -period 10 -name virt_clk_in # Create the input delay referencing the virtual clock and not the base # clock # DO NOT use set_input_delay -clock clk_in <delay value> # [get_ports data_in] set_input_delay -clock virt_clk_in <delay value> [get_ports data_in]