O-RAN Intel® FPGA IP User Guide

Download PDF
ID 683238
Date 2/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP 2. Getting Started with the O-RAN Intel® FPGA IP 3. O-RAN IP Functional Description 4. O-RAN IP Registers 5. O-RAN Intel FPGA IP User Guide Archive 6. Document Revision History for the O-RAN Intel® FPGA IP User Guide
1. About the O-RAN Intel® FPGA IP x
1.1. O-RAN Intel® FPGA IP Features 1.2. O-RAN Intel® FPGA IP Device Family Support 1.3. Release Information for the O-RAN Intel® FPGA IP 1.4. O-RAN Intel® FPGA IP Performance and Resource Utilization
2. Getting Started with the O-RAN Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the O-RAN IP 2.2. Parameterizing the O-RAN IP 2.3. Generated IP File Structure
2.2. Parameterizing the O-RAN IP x
2.2.1. O-RAN IP Parameters
3. O-RAN IP Functional Description x
3.1. O-RAN IP Signals 3.2. O-RAN Intel® FPGA IP Error Handling 3.3. O-RAN Reset Transactions 3.4. O-RAN IP Streaming Mode 3.5. O-RAN IP Performance Counters 3.6. O-RAN IP Transmission and Reception Window Threshold 3.7. O-RAN IP Fragmentation 3.8. O-RAN IP U-Plane Packet Size
3.6. O-RAN IP Transmission and Reception Window Threshold x
3.6.1. O-RAN IP Examples for Transmission and Reception Window Thresholds
1. About the O-RAN Intel® FPGA IP
2. Getting Started with the O-RAN Intel® FPGA IP
3. O-RAN IP Functional Description
4. O-RAN IP Registers
5. O-RAN Intel FPGA IP User Guide Archive
6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

2.2.1. O-RAN IP Parameters

Create custom variations of your IP.
Parameter Name Values Description
RU category A and B RU category A and B are always on.
Maximum Ethernet frame size 1500 or 9000 Specify the maximum Ethernet frame size. When value is greater than 1500, you must supply the packet size. When you select 9000, the IP creates tx_c_size, tx_u_size, and source_pkt_size signals in the transmitter application Interface and transport interface.
Enable 30 kHz subcarrier spacing Off or on Turn off to operate O-RAN window monitor with 15 kHz subcarrier spacing (SCS). Turn on to operate O-RAN window monitor with 30 kHz SCS.
Enable companding Off or on Turn on for compression and decompression for U-plane IQ data.
ulaw compression Off or on

Turn on for µ-law compression and decompression for U-plane IQ data.

This parameter is available when you turn on Enable companding.

This parameter is unavailable when you turn off Enable companding.

You can turn on either or both Block floating-point compression and ulaw compression

Block floating-point compression Off or on Turn on for block floating-point compression and decompression for U-plane IQ data.

This parameter is available when you turn on Enable companding.

This parameter is unavailable when you turn off Enable companding.

You can turn on either or both Block floating-point compression and ulaw compression

Avalon Streaming data width 128 when Enable companding is turned on. 64 when Enable companding is turned off. Specify the Avalon streaming data width.
Enable C plane Off or on Turn on for the C-plane.
Enable U-plane Fragmentation Off or on Turn on for U-plane fragmentation. The ORAN Design Example does not support U-plane fragmentation.
Programmable U-Plane Fragmentation FIFO Depth 512, 1024, 2048

User configurable FIFO depth for U-plane fragmentation.
Enable C-plane Fragmentation Off or on Turn on for C-plane fragmentation. The ORAN Design Example does not support C-plane fragmentation.
Programmable C-Plane Fragmentation FIFO Depth 512, 1024, 2048

User configurable FIFO depth for C-plane fragmentation.
Fragmentation Supported Number of eAxC Channel(s) 0x001 to 0x100 Number of eAxC channels that the fragmentation supports. Set this parameter to the number of unique eAxC IDs you expect from the application layer.
Related Information
Level Two Title