Visible to Intel only — GUID: mwh1409960151404
Ixiasoft
Visible to Intel only — GUID: mwh1409960151404
Ixiasoft
2.7.2. Schematic Symbols
Symbol | Description |
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I/O Ports |
An input, output, or bidirectional port in the current level of hierarchy. A device input, output, or bidirectional pin when viewing the top‑level hierarchy. The symbol can also represent a bus. Only one wire is shown connected to the bidirectional symbol, representing the input and output paths. Input symbols appear on the left-most side of the schematic. Output and bidirectional symbols appear on the right‑most side of the schematic. |
I/O Connectors |
An input or output connector, representing a net that comes from another page of the same hierarchy. To go to the page that contains the source or the destination, double-click the connector to jump to the appropriate page. |
OR, AND, XOR Gates |
An OR, AND, or XOR gate primitive (the number of ports can vary). A small circle (bubble symbol) on an input or output port indicates the port is inverted. |
MULTIPLEXER |
A multiplexer primitive with a selector port that selects between port 0 and port 1. A multiplexer with more than two inputs is displayed as an operator. |
BUFFER |
A buffer primitive. The figure shows the tri-state buffer, with an inverted output enable port. Other buffers without an enable port include LCELL, SOFT, CARRY, and GLOBAL. The NOT gate and EXP expander buffers use this symbol without an enable port and with an inverted output port. |
LATCH |
A latch/DFF (data flipflop) primitive. A DFF has the same ports as a latch and a clock trigger. The other flipflop primitives are similar:
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Atom Primitive |
An atom primitive. The symbol displays the atom name, the port names, and the atom type. The blue shading indicates an atom primitive for which you can view the internal details. |
Other Primitive |
Any primitive that does not fall into the previous categories. Primitives are low-level nodes that cannot be expanded to any lower hierarchy. The symbol displays the port names, the primitive or operator type, and its name. |
Instance |
An instance in the design that does not correspond to a primitive or operator (a user‑defined hierarchy block). The symbol displays the port name and the instance name. |
Encrypted Instance |
A user-defined encrypted instance in the design. The symbol displays the instance name. You cannot open the schematic for the lower-level hierarchy, because the source design is encrypted. |
State Machine Instance |
A finite state machine instance in the design. |
RAM |
A synchronous memory instance with registered inputs and optionally registered outputs. The symbol shows the device family and the type of memory block. This figure shows a true dual-port memory block in a Stratix M-RAM block. |
Constant |
A constant signal value that is highlighted in gray and displayed in hexadecimal format by default throughout the schematic. |
Symbol | Description |
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State Node |
The node representing a state in a finite state machine. State transitions are indicated with arcs between state nodes. The double circle border indicates the state connects to logic outside the state machine, and a single circle border indicates the state node does not feed outside logic. |
Symbol | Description |
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An adder operator: OUT = A + B |
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A multiplier operator: OUT = A ¥ B |
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A divider operator: OUT = A / B |
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Equals |
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A left shift operator: OUT = (A << COUNT) |
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A right shift operator: OUT = (A >> COUNT) |
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A modulo operator: OUT = (A%B) |
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A less than comparator: OUT = (A<:B:A>B) |
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A multiplexer: OUT = DATA [SEL] The data range size is 2sel range size |
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A selector: A multiplexer with one-hot select input and more than two input signals |
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A binary number decoder: OUT = (binary_number (IN) == x) for x = 0 to |