Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Public
Document Table of Contents

7.8.4. Modify the Connectivity between Resource Atoms

The Chip Planner and Resource Property Editor allow you to create new resource atoms and manipulate the existing connection between resource atoms in the post-fit netlist. These features are useful for small changes when you are debugging a design, such as manually inserting pipeline registers into a combinational path that fails timing, or routing a signal to a spare I/O pin for analysis.

Use the following procedure to create a new register in a Cyclone V device and route register output to a spare I/O pin. This example illustrates how to create a new resource atom and modify the connections between resource atoms.

To create new resource atoms and manipulate the existing connection between resource atoms in the post-fit netlist, follow these steps:

  1. Create a new register in the Chip Planner.
  2. Locate the atom in the Resource Property Editor.
  3. To assign a clock signal to the register, right-click the clock input port for the register, point to Edit connection, and click Other. Use the Node Finder to assign a clock signal from your design.
  4. To tie the SLOAD input port to VCC, right-click the clock input port for the register, point to Edit connection, and click VCC.
  5. Assign a data signal from your design to the SDATA port.
  6. In the Connectivity window, under the output port names, copy the port name of the register.
  7. In the Chip Planner, locate a free I/O resource and create an output buffer.
  8. Locate the new I/O atom in the Resource Property Editor.
  9. On the input port to the output buffer, right-click, point to Edit connection, and click Other.
  10. In the Edit Connection dialog box, type the output port name of the register you have created.
  11. Run the ECO Fitter to apply the changes by clicking Check and Save Netlist Changes.
    Note: A successful ECO connection is subject to the available routing resources. You can view the relative routing utilization by selecting Routing Utilization as the Background Color Map in the Layers Settings dialog box of the Chip Planner. Also, you can view individual routing channel utilization from local, row, and column interconnects with the tooltips created when you position your mouse pointer over the appropriate resource. Refer to the device data sheet for more information about the architecture of the routing interconnects of your device.