Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Public
Document Table of Contents

3.5.4. I/O Timing Optimization Techniques

This stage of design optimization focuses on I/O timing, including setup delay (tSU), hold time (tH), and clock-to-output (tCO) parameters.

Before proceeding with I/O timing optimization, ensure that:
  • The design's assignments follow the suggestions in the Initial Compilation: Required Settings section of the Design Optimization Overview chapter.
  • Resource utilization is satisfactory.

You can apply the suggestions this section to all Intel FPGA families and to the family of CPLDs.

Note: Complete this stage before proceeding to the register-to-register timing optimization stage. Changes to the I/O paths affect the internal register-to-register timing.

Summary of Techniques for Improving Setup and Clock-to-Output Times

The table lists the recommended order of techniques to reduce tSU and tCO times. Reducing tSU times increases hold (tH) times.

Note: Verify which options are available to each device family
Table 9.  Improving Setup and Clock-to-Output Times
Order Technique Affects tSU Affects tCO
1 Verify of that the appropriate constraints are set for the failing I/Os (refer to Initial Compilation: Required Settings) Yes Yes
2 Use timing-driven compilation for I/O (refer to Fast Input, Output, and Output Enable Registers) Yes Yes
3 Use fast input register (refer to Programmable Delays) Yes N/A
4 Use fast output register, fast output enable register, and fast OCT register (refer to Programmable Delays) N/A Yes
5 Decrease the value of Input Delay from Pin to Input Register or set Decrease Input Delay to Input Register = ON Yes N/A
6 Decrease the value of Input Delay from Pin to Internal Cells or set Decrease Input Delay to Internal Cells = ON Yes N/A
7 Decrease the value of Delay from Output Register to Output Pin or set Increase Delay to Output Pin = OFF (refer to Fast Input, Output, and Output Enable Registers) N/A Yes
8 Increase the value of Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations (refer to Fast Input, Output, and Output Enable Registers) Yes N/A
9 Use PLLs to shift clock edges Yes Yes
10 Use the Fast Regional Clock (refer to Change How Hold Times are Optimized for MAX® II Devices) N/A Yes
11 For MAX® II or MAX® V family devices, set Guarantee I/O Paths Have Zero Hold Time at Fast Corner to OFF, or When T SU and T PD Constraints Permit (refer to Change How Hold Times are Optimized for MAX® II Devices) Yes N/A
12 Increase the value of Delay to output enable pin or set Increase delay to output enable pin (refer to Use PLLs to Shift Clock Edges) N/A Yes