Nios II Embedded Design Suite Release Notes

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ID 683228
Date 6/17/2015
Public
Document Table of Contents
Document Table of Contents x
1. Nios® II Embedded Design Suite Release Notes
1. Nios® II Embedded Design Suite Release Notes x
1.1. Product Revision History 1.2. Nios II EDS v15.0 Updates 1.3. Nios II EDS v14.1 Updates 1.4. Nios II EDS v14.0 Updates 1.5. Nios II EDS v13.1 Updates 1.6. Known Issues and Errata
1.3. Nios II EDS v14.1 Updates x
1.3.1. Nios II Gen2 Processor Core 1.3.2. New Embedded IPs for 14.1 1.3.3. 64-Bit Host Support Enhanced 1.3.4. Upgrades to the Eclipse Environment 1.3.5. Upgrades to the Nios II GNU Toolchain 1.3.6. Additional Support for Max10 1.3.7. Upgrades to the EPCQ IP Peripheral
1.4. Nios II EDS v14.0 Updates x
1.4.1. 64-Bit Host Support 1.4.2. Run-time Stack Checking 1.4.3. Long Jump Support 1.4.4. Floating Point Hardware 2 Support 1.4.5. Qsys Bridge Support 1.4.6. Nios II Gen2 Processor Support
1.4.6. Nios II Gen2 Processor Support x
1.4.6.1. The Nios II Gen2 Processor Core 1.4.6.2. HAL Support for the Nios II Gen2 Processor 1.4.6.3. Nios II Gen2 Processor and MAX 10 FPGA Support 1.4.6.4. What's New in v14.0a10: the Nios II Gen2 Processor and Arria 10 FPGA Support
1.4.6.3. Nios II Gen2 Processor and MAX 10 FPGA Support x
1.4.6.3.1. Nios II Gen2 Processor Cores and MAX 10 FPGA Support 1.4.6.3.2. Tool Support for the MAX 10 FPGA
1.5. Nios II EDS v13.1 Updates x
1.5.1. GCC Upgraded to 4.7.3 1.5.2. Enhanced Floating Point Custom Instruction Support 1.5.3. ECC Support 1.5.4. Universal Boot Copier
1. Nios® II Embedded Design Suite Release Notes

1.4.6.2. HAL Support for the Nios II Gen2 Processor

The Nios II Hardware Abstraction Layer (HAL) is extended to support the following Nios II Gen2 features:

  • A 32-bit address range
  • Peripheral (uncached) memory regions
  • ECC protection on data cache and TCMs in the Nios II/f core
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