O-RAN Intel® FPGA IP Design Example User Guide

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ID 683218
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP Design Example 2. Getting Started with the O-RAN Intel® FPGA IP Design Example 3. O-RAN Intel® FPGA IP Design Example Functional Description 4. O-RAN IP Design Example User Guide Archives 5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
2. Getting Started with the O-RAN Intel® FPGA IP Design Example x
2.1. Generating the O-RAN IP Design Example 2.2. Simulating the O-RAN IP Design Example 2.3. Operating the O-RAN IP Design Example
2.1. Generating the O-RAN IP Design Example x
2.1.1. O-RAN IP Design Example Parameters
2.2. Simulating the O-RAN IP Design Example x
2.2.1. Simulating the O-RAN Design Example for Intel Agilex® 7 F-Tile Devices 2.2.2. Enabling Dynamic Reconfiguation to the Ethernet IP 2.2.3. O-RAN IP Design Example Testbench
2.3. Operating the O-RAN IP Design Example x
2.3.1. Generating and Downloading the Linking Format .elf Programming File
1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide

2.1. Generating the O-RAN IP Design Example

Quickly configure your custom IP variation in the IP Parameter Editor and generate a design example.
Before you begin, ensure both the eCPRI Intel FPGA IP and ORAN Intel FPGA IP are installed in the <quartus_installation_dir>/ip/altera_cloud directory.
  1. Create an Quartus® Prime Pro Edition project in which to integrate your IP.
    1. In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Intel Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
    2. Specify the device family that meets the speed grade requirements for the IP.
    3. Click Finish.
  2. In the IP Catalog, select O-RAN Intel FPGA IP.
    The New IP Variation window appears.
  3. Specify a top-level name for your new custom IP variation.
    The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
    Figure 1. O-RAN IP Parameter Editor
  5. Specify the parameters for your IP variation. Refer to Parameters for information about specific IP parameters.
    The O-RAN Design Example does not support window monitoring or application layer fragmentation.
  6. Click the Design Example tab and specify the parameters for your design example.
    Figure 2. Design Example Parameter Editor
  7. Click Generate HDL.
    The Generation dialog box appears.
  8. Specify output file generation options, and then click Generate.
    The IP variation files generate according to your specifications.
  9. Click Finish. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  10. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports and set any appropriate per-instance RTL parameters.

Section Content
O-RAN IP Design Example Parameters

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