50G Interlaken MegaCore Function User Guide

ID 683217
Date 9/20/2022
Public

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5.1. 50G Interlaken IP Core Clock Interface Signals

Table 11.   50G Interlaken IP Core Clock Interface

Signal Name

Direction

Width (Bits)

Description

Clock Ports

pll_ref_clk

Input

1

Transceiver reference clock for the RX CDR PLL in IP core variations that target an Intel® Arria® 10 device. Transceiver reference clock for the RX CDR PLL and the TX transceiver PLL in all other variations.

The 50G Interlaken IP core supports the following pll_ref_clk frequencies: 156.25 MHz, 195.3125 MHz, 250 MHz, 312.5 MHz, 390.625 MHz, 500 MHz, and 625 MHz.

The pll_ref_clk input clock frequency must match the value you specify for the Transceiver reference clock frequency parameter.

tx_serial_clk

Input

NUM_LANES–

Clocks for the individual transceiver channels in 50G Interlaken IP core variations that target an Intel® Arria® 10 device.

clk_tx_common

Output

1

PCS common lane clock driven by the SERDES transmit PLL. The clock rate is the lane rate divided by 40 bits. The clk_tx_common frequency is 156.25 MHz for 6.25 Gbps per lane.

clk_rx_common

Output

1

Master recovered lane clock. The Interlaken specification requires all incoming lanes to run at the same frequency.

tx_usr_clk

Input

1

Transmit side user data interface clock. To achieve 40 Gbps Ethernet traffic throughput, you must run this clock at a minimum frequency of 200 MHz.

By default, you must drive this clock at 250 MHz. To change the input clock frequency, you must first modify the value of the TX_USR_CLK_MHZ advanced parameter to the new frequency. The allowed range of frequencies you can specify is 200 MHz to 300 MHz.

rx_usr_clk

Input

1

Receive side user data interface clock. To achieve 40 Gbps Ethernet traffic throughput, you must run this clock at a minimum frequency of 200 MHz.

By default, you must drive this clock at 250 MHz. To change the input clock frequency, you must first modify the value of the TX_USR_CLK_MHZ advanced parameter to the new frequency. The allowed range of frequencies you can specify is 200 MHz to 300 MHz.

mm_clk

Input

1

Management clock. Clocks the register accesses. It is also used for clock rate monitoring and some analog calibration procedures. You must run this clock at a frequency in the range of 100 MHz–125 MHz.

reconfig_clk

Input

1 Clocks the Intel® Arria® 10 transceiver reconfiguration interface. This clock is available only in IP core variations that target an Intel® Arria® 10 device. You should run this clock at a frequency of 100 MHz.
Note: If you change the port name or period of a clock, then you must modify .sdc file to match the corresponding changes.