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1. About This IP Core
2. Getting Started With the 50G Interlaken IP Core
3. 50G Interlaken IP Core Parameter Settings
4. Functional Description
5. 50G Interlaken IP core Signals
6. 50G Interlaken IP Core Register Map
7. 50G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 50G Interlaken IP core
10. 50G Interlaken IP core User Guide Archives
11. Document Revision History for 50G Interlaken User Guide
A. Performance and Fmax Requirements for 40G Ethernet Traffic
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 50G Interlaken IP Core Parameters and Options
2.3. Files Generated for Arria V GZ and Stratix V Variations
2.4. Files Generated for Intel® Arria® 10 Variations
2.5. Simulating the 50G Interlaken IP Core
2.6. Integrating Your IP Core in Your Design
2.7. Compiling the Full Design and Programming the FPGA
2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
5.1. 50G Interlaken IP Core Clock Interface Signals
5.2. 50G Interlaken IP Core Reset Interface Signals
5.3. 50G Interlaken IP Core User Data Transfer Interface Signals
5.4. 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
5.5. 50G Interlaken IP Core Management Interface
5.6. Device Dependent Signals
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2.6.4. Adding the External PLL
50G Interlaken IP core variations that target an Arria 10 device require an external transceiver PLL to function correctly in hardware. 50G Interlaken IP core variations that target an Arria V or Stratix V device include the transceiver PLLs and do not require that you configure any additional PLLs.
You can use the IP Catalog to generate an external PLL IP core that configures a TX PLL on the device.
- Select Intel® Arria® 10 Transceiver ATX PLL, Intel® Arria® 10 Transceiver CMU PLL, or Intel® Arria® 10 FPLL.
- In the parameter editor, set the following parameter values:
- PLL output frequency to one half the per-lane data rate of the IP core variation. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting drives the transceiver with the correct clock for the Interlaken lanes.
- PLL reference clock frequency to a frequency at which you can drive the TX PLL input reference clock. You must drive the external PLL reference clock input signal at the frequency you specify for this parameter.
The number of external PLLs you must define depends on the distribution of your Interlaken TX serial lines across physical transceiver channels. You specify the clock network to which each PLL output connects by setting the clock network in the PLL parameter editor.
You must connect the external PLL signals and the Intel® Arria® 10 50G Interlaken IP core transceiver Tx PLL interface signals according to the following rules:
- Connect the tx_serial_clk input pin for each Interlaken lane to the output port of the same name in the corresponding external PLL.
- Connect the tx_pll_locked input pin of the 50G Interlaken IP core to the logical AND of the pll_locked output signals of the external PLLs for all of the Interlaken lanes and the inverse of each of the pll_cal_busy signals from the external PLLs.
- Connect the tx_pll_powerdown output pin of the 50G Interlaken IP core to the pll_powerdown reset pin of the external PLLs for all of the Interlaken lanes.
User logic must provide the AND function and connections. The following figure provides an example of one correct method, among many, to implement connection logic. You can also refer to the example design for example working user logic including one correct method to instantiate and connect an external PLL.
Figure 7. Example Connection of ATX PLL with 50G Interlaken IP Core Using Intel® Arria® 10 xN Clock Network