Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GT FPGA Datasheet

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ID 683214
Date 11/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. FPGA Factory Image 7. Board Management Controller A. References B. Document Revision History for Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GT FPGA Datasheet
2. Overview x
2.1. Intel® PAC with Intel® Arria® 10 GT FPGA Block Diagram 2.2. Overview of Product Features
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GT FPGA 2.2.2. Fortville Network Interface Controller 2.2.3. On-Board Memory 2.2.4. Interfaces and Dimensions 2.2.5. Software 2.2.6. Power 2.2.7. Board Management Controller (BMC) 2.2.8. Network Interface 2.2.9. Control and Support
2.2.9. Control and Support x
2.2.9.1. Parkvale Retimer 2.2.9.2. PCIe Overview 2.2.9.3. Board Management Controller Overview
5. Thermal Specifications x
5.1. Thermal Test Performance Results
7. Board Management Controller x
7.1. BMC Features
7.1. BMC Features x
7.1.1. BMC Voltage and Thermal Handling
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. FPGA Factory Image
7. Board Management Controller
A. References
B. Document Revision History for Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GT FPGA Datasheet

7.1. BMC Features

The on-board microcontroller:
  • Provides low-level access to board features.
  • Interfaces with sensors, FPGA, flash and QSFP.
  • Controls power and resets on the board.
  • Monitors temperatures, voltages and currents and provides protective action when readings are outside of critical thresholds.
  • Provides Platform Level Data Model (PLDM) for PCIe I2C communication. The I2C slave address is 0xCE.
Figure 5. Board Management Controller for the Intel® PAC with Intel® Arria® 10 GT FPGA
Level Two Title