Intel Programmable Acceleration Card (PAC) with Intel Arria 10 GT FPGA Datasheet

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ID 683214
Date 11/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. FPGA Factory Image 7. Board Management Controller A. References B. Document Revision History for Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GT FPGA Datasheet
2. Overview x
2.1. Intel® PAC with Intel® Arria® 10 GT FPGA Block Diagram 2.2. Overview of Product Features
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GT FPGA 2.2.2. Fortville Network Interface Controller 2.2.3. On-Board Memory 2.2.4. Interfaces and Dimensions 2.2.5. Software 2.2.6. Power 2.2.7. Board Management Controller (BMC) 2.2.8. Network Interface 2.2.9. Control and Support
2.2.9. Control and Support x
2.2.9.1. Parkvale Retimer 2.2.9.2. PCIe Overview 2.2.9.3. Board Management Controller Overview
5. Thermal Specifications x
5.1. Thermal Test Performance Results
7. Board Management Controller x
7.1. BMC Features
7.1. BMC Features x
7.1.1. BMC Voltage and Thermal Handling
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. FPGA Factory Image
7. Board Management Controller
A. References
B. Document Revision History for Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GT FPGA Datasheet

1. Introduction

Figure 1.  Intel® Programmable Acceleration Card with Intel® Arria® 10 GT FPGA

This datasheet describes the Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GT FPGA, featuring the Intel® Arria® 10 GT FPGA. This document shows electrical, mechanical, compliance, and other key specifications. This datasheet assists network operators and system integrators to properly deploy this PAC into their servers. It also documents the FPGA power envelope, connectivity speeds to memory, and network connectivity, so that accelerator function unit (AFU) developers can properly design and test their IP.

The PAC is supported by the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs. The Intel® Acceleration Stack provides a common developer interface to both application and acceleration function developers and includes drivers, Application Programming Interfaces (APIs) and an FPGA factory image.

For information about using the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs, refer to the Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GT FPGA .
Note: Contact your Intel field sales representative for EAP documentation for the Intel PAC with Intel Arria 10 GT FPGA.

Along with acceleration libraries and development tools, the Acceleration Stack saves development time and enables code re-use across multiple Intel FPGA form-factor products, allowing the developer to focus on the unique value-addition of their solution.

Intel validates each Intel® Programmable Acceleration Card with Intel® Arria® 10 GT FPGA to support large scale deployments requiring FPGA acceleration. This platform is targeted for market-specific acceleration in applications such as:

  • Network Function Virtualization (NFV)
  • Multi-Access Edge Computing (MEC)
  • Video Transcoding
  • Cyber Security
  • High-Performance Computing
  • Finance
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