SDI II Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683209
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide

1.4. Simulating the Design

The SDI II Intel® FPGA IP design example testbench simulates one channel serial loopback design with TX instance connected to an internal video pattern generator. The serial output from the TX instance connects to the RX instance in the testbench. The testbench also includes checkers and control mechanisms.
Figure 4. Design Simulation Flow
  1. Navigate to the simulation folder of your choice.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
    Table 3.  Steps to Run Simulation
    Simulator Working Directory Instructions
    Riviera-PRO* /simulation/aldec
    In the GUI, type: 
    do aldec.do
    Xcelium* /simulation/xcelium
    In the command line, type: 
    source xcelium_sim.sh
    ModelSim* /simulation/mentor
    In the GUI, type: 
    do mentor.do
    VCS* /simulation/synopsys/vcs
    In the command line, type: 
    source vcs_sim.sh
    VCS* MX /simulation/synopsys/vcsmx
    In the command line, type: 
    source vcsmx_sim.sh
    A successful simulation ends with the following message: 
    #### TRANSMIT TEST COMPLETED SUCCESSFULLY! ####
#  
#### Channel 1: RECEIVE TEST COMPLETED SUCCESSFULLY! ####
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