SDI II Intel® Arria 10 FPGA IP Design Example User Guide

Download PDF
ID 683209
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel® FPGA IP Design Example Detailed Description x
Features 2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide

2. SDI II Intel® FPGA IP Design Example Detailed Description

The SDI II Intel® FPGA IP core includes these design examples for Intel® Arria® 10 devices.
  • Parallel loopback with external VCXO
  • Parallel loopback without external VCXO
  • Serial loopback

Features

  • For HD/3G-SDI single rate and triple rate designs, you can choose either CMU or fPLL as the TX PLL.
  • All designs use LED status for early debugging stage.
  • The simplex serial loopback designs include RX and TX options. To use RX or TX only components, remove the irrelevant blocks from the designs.
    User Requirement Preserve Remove
    RX Only RX Top
    • TX Top
    • Transceiver Arbiter
    TX Only TX Top
    • RX Top
    • Transceiver Arbiter
    Note: You can directly connect the Avalon-MM pins at the RX or TX Top as shown in the diagram below.
Figure 7. Components Required for Intel® Arria® 10 TX or RX Only Design
Level Two Title