SDI II Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683209
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide

1.5.2. Design Considerations

You need to consider certain issues when instantiating the SDI II Intel® FPGA IP design examples.

  • For designs using simplex receivers:
    • The simplex receiver channel may not calibrate correctly if its corresponding unused transmitter is preserved. Simplex receiver channels with the corresponding transmitters not preserved calibrate correctly. To overcome this issue, make the following changes in the QSF file.
      Remove the global preservation QSF assignment 
      set_global_assignment –name PRESERVE_UNUSED_XCVR_CHANNEL ON
      Add per-pin preservation QSF assignment 
      set_instance_assignment –name PRESERVE_UNUSED_XCVR_CHANNEL ON –to <pin name>
  • Serial loopback designs:
    • The serial loopback design is mainly for image and TX clock switching demonstrations only. To get a more accurate jitter performance with the daughter card components, use the parallel loopback design and connect it to a clean video source.
    • To allow segmented frame video format (1080sF30, 1080sF25) and interlaced video format (1080i60, 1080i50) to be correctly differentiated in the external analyzer, Payload ID must be inserted in the serial loopback design.
    • The Omnitek Ultra 4K Analyzer (software version 2.1) may not detect 12G-SDI 2160p59.94 in the serial loopback design. If you encounter such problem, upgrade the Omnitek Ultra 4K analyzer to a later version.
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