SDI II Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683209
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines Connections and Settings for HD/3G-SDI Single Rate and Triple Rate Designs Connections and Settings for Multi Rate Design 1.5.2. Design Considerations
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide

1.5.1. Connection and Settings Guidelines

Before programing with the .sof file, ensure that the connections and settings are correct.

Connections and Settings for HD/3G-SDI Single Rate and Triple Rate Designs

  • For parallel loopback design, the on-board SMB RX connector (J20) connects to an external video source and the on-board SMB TX connector (J21) connects to a video analyzer.
  • For serial loopback design, the on-board SMB TX connector (J21) connects to an on-board SMB RX connector (J20) or a video analyzer.
  • Ensure all switches on the development board are in default position.
  • The SDI video analyzer displays the video generated from the source.
    Note: For parallel loopback designs, you may need to switch the Si516_FS (SW6.3) at the back of the board if you are switching between fractional frame rate and integer frame rate video format.
Figure 5. Switch Settings on the Arria 10 Development Board
Table 4.  SW6 DIP Switch Default Settings (Bottom of the Board)
Switch Board Label Description
1 CLK_SEL
  • ON for 100 MHz on-board clock oscillator selection (Default position)
  • OFF for SMA input clock selection
2 CLK_EN OFF for setting CLK_ENABLE high to the MAX V
3 SI516_FS
  • ON for setting the SDI REFCLK frequency to 148.35 MHz
  • OFF for setting the SDI REFCLK frequency to 148.5 MHz (Default position)
4 FACTORY
  • ON to load factory from flash (Default position)
  • OFF to load user hardware from flash
5 RZQ_B2K
  • ON for setting RZQ resistor of Bank 2K to 99.17 ohm
  • OFF for setting RZQ resistor of Bank 2K to 240 ohm (Default position)

Connections and Settings for Multi Rate Design

  • A VIDIO™ FMC Development Module VIDIO-12G-A (Nextera 12G SDI FMC daughter card) connects to the FMC Port B on the development board.
  • For parallel loopback design, the BNC RX connector (J1/12G In) connects to an external video source and the TX connector (J2/12G Out) connects to a video analyzer.
  • For serial loopback design, the BNC TX connector (J2/12G Out) connects to the BNC RX connector (J1/12G In) or a video analyzer.
  • Ensure all switches on the development board are in default position.
  • The SDI video analyzer displays the video generated from the source.
    Note: Change the jumper (J8) position before switching between fractional frame rate and integer frame rate video formats. Press the push button (PB0) to trigger a device (LMK03328) power cycling through the PDN pin every time you change the jumper (J8) position.
Figure 6. Jumper Settings on Nextera 12G-SDI FMC Daughter CardRefer to these settings to change the jumper (J8) position.
Table 5.  Jumper Settings
Jumper Block Description
J7 Programming header
J8 To switch the generated clock frequency for the TX channel:
  • Pin 1–2 = 297 MHz
  • Pin 2–3 = 297/1.001 MHz
J9 To select SDI or IP mode:
  • Pin 1–2 = SDI mode
  • Pin 2–3 = IP mode
Related Information
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