FIR II IP Intel® FPGA IP: User Guide

ID 683208
Date 9/17/2024
Public
Document Table of Contents

3.5.1.1. Using Memory Block Threshold

This FIR II IP threshold is the trade-off between simple delay LEs and small ROM blocks. If any delay’s size is such that the number of LEs is greater than this parameter, the IP implements delay as RAM blocks .
  1. To make more delays usememory blocks, enter a lower number, such as a value in the range of 20–30.
  2. To use fewer memory blocks, enter a larger number, such as 100.
  3. To never use a memory block memory for simple delays, enter a very large number, such as 10000.
  4. Implement delays of less than three cycles in LEs because of memory block behavior.
    Note: This threshold only applies to implementing simple delays in memory blocks or LEs. You cannot push dual memories back into LEs.