FIR II IP Intel® FPGA IP: User Guide

ID 683208
Date 9/17/2024
Public
Document Table of Contents

3.5.1.3. Using Large RAM Threshold

This FIR II IP core threshold is the trade-off between medium and large RAM blocks. For larger delays, implement memory in medium-block RAM (M4K, M9K) or use larger M-RAM blocks (M512K, M144K).
  1. Set the number of bits in a memory or delay greater than this threshold, to use M-RAM.
  2. Set a large value such as the default of 1,000,000 bits, to never use M-RAM blocks.