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4.1. FIR II IP Core Interpolation Filters
4.2. FIR Decimation Filters
4.3. FIR II IP Time-Division Multiplexing
4.4. FIR II IP Core Multichannel Operation
4.5. FIR II IP Multiple Coefficient Banks
4.6. FIR II IP Coefficient Reloading
4.7. Reconfigurable FIR Filters
4.8. FIR II IP Core Interfaces and Signals
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1.4. DSP Intel® FPGA IP Verification
Before releasing a version of an IP, Intel runs comprehensive regression tests to verify its quality and correctness. Intel generates custom variations of the IP to exercise the various parameter options and thoroughly simulates the resulting simulation models with the results verified against master simulation models.