FIR II IP Core: User Guide

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ID 683208
Date 8/14/2023
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Document Table of Contents
Document Table of Contents x
1. About the FIR II IP Core 2. FIR II IP Core Getting Started 3. FIR II IP Core Parameters 4. FIR II IP Core Functional Description 5. Document Revision History for the FIR II IP User Guide A. FIR II IP Core Document Archive
1. About the FIR II IP Core x
1.1. DSP Intel® FPGA IP Features 1.2. FIR II IP Core Features 1.3. FIR II IP Device Support 1.4. DSP Intel® FPGA IP Verification 1.5. FIR II IP Core Release Information 1.6. FIR II IP Core Performance and Resource Utilization
2. FIR II IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the FIR II IP Core Testbench in MATLAB 2.6. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FIR II IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. FIR II IP Core Parameters x
3.1. FIR II IP Core Filter Specification 3.2. FIR II IP Core Coefficient Settings 3.3. FIR II IP Core Coefficients 3.4. FIR II IP Core Input and Output Options 3.5. FIR II IP Core Implementation Options 3.6. FIR II IP Core Reconfigurability
3.3. FIR II IP Core Coefficients x
3.3.1. Loading Coefficients from a File
3.4. FIR II IP Core Input and Output Options x
3.4.1. Signed Fractional Binary 3.4.2. MSB and LSB Truncation, Saturation, and Rounding
3.5. FIR II IP Core Implementation Options x
3.5.1. Memory and Multiplier Trade-Offs
3.5.1. Memory and Multiplier Trade-Offs x
3.5.1.1. Using Memory Block Threshold 3.5.1.2. Using Dual-port RAM Threshold 3.5.1.3. Using Large RAM Threshold 3.5.1.4. Using Hard Multiplier Threshold
4. FIR II IP Core Functional Description x
4.1. FIR II IP Core Interpolation Filters 4.2. FIR Decimation Filters 4.3. FIR II IP Core Time-Division Multiplexing 4.4. FIR II IP Core Multichannel Operation 4.5. FIR II IP Core Multiple Coefficient Banks 4.6. FIR II IP Core Coefficient Reloading 4.7. Reconfigurable FIR Filters 4.8. FIR II IP Core Interfaces and Signals
4.4. FIR II IP Core Multichannel Operation x
4.4.1. Vectorized Inputs 4.4.2. Channelization 4.4.3. Channel Input and Output Format
4.4.3. Channel Input and Output Format x
4.4.3.1. Eight Channels on Three Wires 4.4.3.2. Four Channels on Four Wires 4.4.3.3. 15 Channels with 15 Valid Cycles and 17 Invalid Cycles 4.4.3.4. 22 Channels with 11 Valid Cycles and 9 Invalid Cycles 4.4.3.5. Super Sample Rate
4.8. FIR II IP Core Interfaces and Signals x
4.8.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.8.2. FIR II IP Core Avalon-ST Interfaces 4.8.3. FIR II IP Core Signals
4.8.2. FIR II IP Core Avalon-ST Interfaces x
4.8.2.1. Avalon-ST Sink Interface 4.8.2.2. Avalon-ST Source Interface
4.8.2.1. Avalon-ST Sink Interface x
4.8.2.1.1. Single Channel on Single Wire 4.8.2.1.2. Multiple Channels on Single Wire 4.8.2.1.3. Multiple Channels on Multiple Wires
1. About the FIR II IP Core
2. FIR II IP Core Getting Started
3. FIR II IP Core Parameters
4. FIR II IP Core Functional Description
5. Document Revision History for the FIR II IP User Guide
A. FIR II IP Core Document Archive

3.5. FIR II IP Core Implementation Options

Table 13.  Implementation Options Parameters
Parameter Value Description
Resource Optimization Settings
Device Family Menu of supported devices The target device family.
Speed grade Fast, medium, slow The speed grade of the target device to balance the size of the hardware against the resources required to meet the clock frequency.
Memory Block Threshold Integer The balance of resources between LEs and small RAM block threshold in bits.
Dual Port RAM Threshold Integer The balance of resources between small and medium RAM block threshold in bits.
Large RAM Threshold Integer The balance of resources between medium and large RAM block threshold in bits.
Hard Multiplier Threshold Integer The balance of resources between LEs and DSP block multiplier threshold in bits. The default value is -1.
Resource Estimation
Number of LUTs - Shows the number of LUTs.
Number of DSPs - Shows the number of DSPs.
Number of memory bits - Shows the number of memory bits.

Section Content
Memory and Multiplier Trade-Offs

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