AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

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ID 683191
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines x
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core 1.2. Migration Flow 1.3. AN 735 Document Revision History
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core x
1.1.1. Architecture Overview 1.1.2. Clock and Reset Scheme 1.1.3. Interface Signals
1.2. Migration Flow x
1.2.1. Instantiating Low Latency Ethernet MAC IP Core 1.2.2. Generating 156.25 MHz and 312.5 MHz Clock 1.2.3. Connecting the Low Latency Ethernet 10G MAC to Avalon-ST, Avalon-MM, and XGMII PHY Interfaces
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

1.2.1. Instantiating Low Latency Ethernet MAC IP Core

Follow these steps to instantiate the Low Latency Ethernet 10G MAC IP core to replace the existing 10GbE MAC IP core in your system design.
  1. Select and instantiate the Low Latency Ethernet 10G MAC IP core from the MegaWizard Plug-In Manager or IP Catalog.
  2. In the Low Latency Ethernet 10G MAC parameter editor, select the same MAC variant used in the existing 10GbE MAC IP core in the user system design.
  3. In the Low Latency Ethernet 10G MAC parameter editor, turn on the following parameters to enable all the adapters in the MAC interface:
    • For Quartus II version 14.1 or before: Under 64-bit Ethernet MAC Interfaces, select Use 64-bit Ethernet 10G MAC XGMII Interface , Use 64-bit Ethernet 10G MAC Avalon Memory-Mapped Interface and Use 64-bit Ethernet 10G MAC Avalon Streaming interface.
    • For Quartus II version 15.0 onwards: Under Legacy Ethernet 10G MAC Interfaces, select Use legacy Ethernet 10G MAC XGMII Interface , Use legacy Ethernet 10G MAC Avalon Memory-Mapped Interface and Use legacy Ethernet 10G MAC Avalon Streaming interface.
  4. Click Finish or Generate to generate all the necessary files to synthesize the IP core.
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