1.1.2. Clock and Reset Scheme
To support 32-bit data bus width for user interface and 32-bit XGMII data bus width for PHY interface, the transmit and receive clock for the Low Latency Ethernet 10G MAC IP core is increased from 156.25 MHz to 312.5 MHz.
However, you are required to supply 156.25 MHz of transmit and receive clock to the Low Latency Ethernet 10G MAC when the 64-bit Avalon-ST adapters, Avalon-MM adapter, and 64-bit XGMII adapters are enabled in the IP core.
The Low Latency Ethernet 10G MAC IP core provides reset signals for the TX datapath, RX datapath, and register configuration path. The reset signal for TX datapath resets both the 312.5 MHz and 156.25 MHz clock domains. The same applies for the RX datapath. Refer to the Low Latency Ethernet 10G MAC IP user guide for more description on the reset signals for this IP core.
Figure 3. Clock and Reset Scheme of 10GbE MAC IP Core Connected to 10GBASE-KR PHY IP CoreThis figure shows an example of the clock and reset scheme of the 10-Gbps Ethernet MAC IP core connected to the 10GBASE-KR PHY IP core.
Figure 4. Clock and Reset Scheme of Low Latency Ethernet 10G MAC Connected to Altera 10GBASE-KR PHY IP Core for Stratix V and Arria V DevicesThis figure shows an example of the clock and reset scheme of the Low Latency Ethernet 10G MAC IP core connected to the 10GBASE-KR PHY IP core with all adapters enabled in the Stratix V or Arria V devices. Additional clock signals are highlighted in blue.
Figure 5. Clock and Reset Scheme of Low Latency Ethernet 10G MAC IP Core Connected to Altera 10GBASE-KR PHY IP Core for Arria 10 DevicesThis figure shows an example of the clock and reset scheme of the Low Latency Ethernet 10G MAC IP core connected to the 10GBASE-KR PHY IP core with all adapters enabled in the Arria 10 device. Additional clock signals are highlighted in blue.