High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

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ID 683189
Date 1/20/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. Introduction to High Bandwidth Memory 3. Intel® Stratix® 10 HBM2 Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface 7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance 8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives 9. Document Revision History for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2 in Intel® Stratix® 10 Devices 2.2. HBM2 DRAM Structure 2.3. Intel® Stratix® 10 HBM2 Features 2.4. Intel® Stratix® 10 HBM2 Controller Features
3. Intel® Stratix® 10 HBM2 Architecture x
3.1. Intel® Stratix® 10 HBM2 Introduction 3.2. Intel® Stratix® 10 UIB Architecture 3.3. Intel® Stratix® 10 HBM2 Controller Architecture
3.3. Intel® Stratix® 10 HBM2 Controller Architecture x
3.3.1. Intel® Stratix® 10 HBM2 Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
4.1. Creating an Intel® Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.3. Pin Planning for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.6. Register Map IP-XACT Support for HBM2 IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design 5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa* 5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS* 5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO* 5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator 5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency 5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface x
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram 6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals 6.3. User AXI Interface Timing 6.4. User APB Interface Timing 6.5. User-controlled Accesses to the HBM2 Controller 6.6. Soft AXI Switch
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals x
6.2.1. Clock Signals 6.2.2. Reset Signals 6.2.3. Calibration Status Signals 6.2.4. Memory Interface Signals 6.2.5. User-interface Signals 6.2.6. AXI User-interface Signals 6.2.7. Sideband APB Interface 6.2.8. Avalon® Memory-Mapped (AVMM) Interface Signals
6.3. User AXI Interface Timing x
6.3.1. AXI Write Transaction 6.3.2. AXI Read Transaction 6.3.3. Improving User Logic to HBM2 Controller AXI Interface Timing
6.4. User APB Interface Timing x
6.4.1. Advanced Peripheral Bus Protocol 6.4.2. APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller x
6.5.1. User-controlled Refreshes 6.5.2. Temperature and Calibration Status Readout 6.5.3. Controller Idle State Status 6.5.4. Power Down Status 6.5.5. ECC Error Status 6.5.6. User Interrupt 6.5.7. ECC Error Correction and Detection
6.5.6. User Interrupt x
6.5.6.1. Interrupt Enable and Conditions for Interrupt Generation 6.5.6.2. Interrupt Status 6.5.6.3. Error Valid Status
6.6. Soft AXI Switch x
6.6.1. AXI Switch Selection in HBM2 IP Catalog GUI
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance x
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth 7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency 7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency 7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing 7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Intel® Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP

The parameter editor contains one Controller tab for each memory channel that you specify on the General tab. The Controller tab allows you to select the HBM2 controller options that you want to enable.
Figure 9. Controller Tab
Table 11.  Group: Controller/ Controller 0 Configuration
Note: When you enable the AXI Switch option, the controller configurations for the corresponding two HBM2 channels should use the same AXI Data Configuration and Enable Re-order buffer options.
Display Name Description
Is clone of Set this option to make this controller a clone of the selected controller. Parameters are copied from the specified controller. This parameter applies when you select more than one HBM2 controller. Set this parameter if you want one controller to have the same settings as another.
Interface Protocol AXI or AVMM ( Avalon® memory-mapped) is displayed, based on the interface protocol that you select for the channel on the General tab.
Enable Auto Precharge Control Select this parameter to enable the auto-precharge control on the controller top level. If you assert the auto-precharge control signal while requesting a read or write burst, you can specify whether the controller should close (auto-precharge) the currently open page at the end of the read or write burst, potentially making a future access to a different page of the same bank faster. Applicable to Avalon® -MM channel only.
Enable Command Priority Control Select this parameter to enable user-requested command priority control on the controller top level. This parameter instructs the controller to treat a read or write request as high-priority. The controller attempts to fill high priority requests sooner, to reduce latency. Connect this interface to the conduit of your logic block that determines when the external memory interface IP treats the read or write request as a high priority command. Applicable to Avalon-MM channel only.
Enable Re-order buffer Specifies that read data be reordered to match the order in which transactions are issued. If you disable this feature, the Read Data provided at the AXI Interface is not expected to follow the same order in which the Read Requests were issued. You can then reorder the data, based on the AXI read ID of the transaction.

This parameter applies to cases with multiple AXI transaction IDs. By using different AXI read/write IDs, you allow the HBM2 controller to reorder transactions for better efficiency. If you use the same AXI ID for all transactions, the controller issues the commands to memory in the order in which they arrive; in this instance, you need not enable the reorder buffer.

Enable AXI interface throttling based on temperature Enables temperature-based throttling for this channel. You can specify the threshold temperature and throttling ratio on the General tab. Enables AXI thermal throttling for the specific HBM2 controller. The parameter that sets the trigger temperature for thermal throttling resides on the General tab. When the temperature of the HBM2 stack reaches the threshold temperature for HBM2 throttling as set on the General tab, the HBM2 controller begins to throttle user requests.
Address reordering Describes the mapping of AXI address to HBM address. Specifies the pattern for mapping from the AXI interface to the HBM2 memory device. By choosing the right address reordering configuration, you help to improve the efficiency of accesses to the HBM2 memory device, based on user traffic pattern. The HBMC supports three types of address reordering:

Address order (32B access: pseudo-BL8 disabled):

SID-BG-BANK-ROW-COL[5:1]
SID-ROW-BANK-COL[5:1]-BG
ROW-SID-BANK-COL[5:1]-BG 
COL[0]=0

Address order (64B access (pseudo-BL8 enabled): 

SID-BG-BANK-ROW-COL[5:1]
SID-ROW-BANK-COL[5:2]-BG-COL[1]
ROW-SID-BANK-COL[5:2]-BG-COL[1]
COL[1:0] = {00})

SID applies only to the 8GB/8H HBM2 devices and is not available for 4GB/4H devices.

Note: The SID-BG-BANK-ROW-COL[5:1] address order limits HBM throughput when memory accesses are sequential, and also affects random access throughput in pseudo-BL8 mode.
User Read Auto-Precharge Policy Describes the policy for determining whether to issue auto-precharge. FORCED indicates that the controller follows the user auto-precharge request exactly. HINT indicates that the controller may override the auto-precharge request by disabling it when a page hit is detected (that is, if it receives two commands, one with auto-precharge and one without auto-precharge to the same page, the controller changes auto-precharge for the first to 0 so that the second can access the page without reopening it). You can issue the request to precharge together with the read command, through the axi_x_y_aruser input, where x denotes the HBM2 channel number (0-7) and y denotes the HBM2 Pseudo Channel number (0/1).

You can choose between two values for this parameter:

  • RDAP_FORCED mode, in which the HBM2 controller implements a user-requested auto-precharge command.
  • RDAP_HINT mode, in which the controller determines when to issue an auto-precharge command, based on user-issued auto-precharge input and the address specified. (Applicable to the AXI user interface mode only.)
User Write Auto-Precharge Policy Describes the policy for determining whether to issue auto-precharge. FORCED indicates that the controller follows the user auto-precharge request exactly. HINT indicates that the controller may override the auto-precharge request by disabling it when a page hit is detected (that is, if it receives two commands, one with auto-precharge and one without auto-precharge to the same page, the controller changes auto-precharge for the first to 0 so that the second can access the page without reopening it). You can issue a precharge request together with the write command, through the axi_x_y_awuser input, where x denotes the HBM2 channel number (0-7) and y denotes the HBM2 Pseudo Channel number (0/1).

You can choose between two values for this parameter:

  • WRAP_FORCED mode, in which the HBM2 controller implements a user-requested auto-precharge command.
  • WRAP_HINT mode, in which the controller determines when to issue an auto-precharge command, based on user-issued auto-precharge input and the address specified. (Applicable to the AXI user interface mode only.)
Power Down Enable Causes the controller to power down when idle.
Refresh mode Specifies the method of controlling refreshes to the high bandwidth memory. User refresh modes are initiated with an access on the Advanced Peripheral Bus (APB). You can choose one of three values for this parameter:
  • The default value is Controller refresh all, which allows the controller to decide when to issue refresh requests.
  • The User refresh all mode issues commands to all banks that correspond to an HBM2 Pseudo-Channel. User refresh all follows the APB protocol; the request must be addressed to one Pseudo-Channel at a time. A user-controlled refresh example is enabled in the design example when you select the User refresh all mode.
  • The User refresh per-bank mode issues commands to a specific bank that corresponds to an HBM2 Pseudo-Channel. User refresh per-bank follows the APB protocol; the request must be addressed to one Pseudo-Channel at a time.
Enable AXI Burst length of more than 2 When this option is enabled, the HBM2 IP supports sequential burst transactions at the AXI Interface. This feature is applicable to AXI channel without switch enabled only. This option enables you to use the AWLEN/ARLEN inputs of the AXI interface and issue sequential burst traffic. The burst size is defined by by the value provided by AWLEN/ARLEN in the burst length 4 mode. You can select this option only when using the BL4 mode at the HBM2 DRAM.
AXI Maximum burst length Maximum of 256 is supported when the enable more than 2 Burst length option is enabled. If the option is disabled, a default value of 1 is set. The maximum burst length value determines the width of the awid/arid. Refer to the AXI Interface Signals section for more details.
Enable Pseudo BL8 for performance

If enabled, data access granularity is 64B (64 bits per Pseudo-Channel at BL8) which can achieve greater efficiency. Otherwise data access granularity is 32B (64 bits per Pseudo-Channel at BL4).

The controller sets the memory transactions burst length based on this setting and ignores the input provided on the user-driven axi_awsize and axi_arsize signals on the AXI interface.

Data width per Pseudo-Channel

Data width per Pseudo Channel. The available data widths are:

256 bits - This refers to 256-bit data transfers at the AXI interface. ECC or write data mask option is available in this data width mode only.

288 bits - This refers to 288-bit data transfers at the AXI interface. ECC or write data mask option is not available in this mode. You must implement your own ECC logic when choosing this data width option.

Memory channel ECC generation and checking/correction

Memory Channel ECC generation and checking / correction. The HBM2 controller supports single-bit error correction and double-bit error detection. This feature is available only when you select the 256-bit data width mode.

The controller does not support write data mask in ECC generation mode.

Write data mask enable Enables the write data mask (DM) input to the HBM2 DRAM.

When you use the DM pins, you cannot use ECC. This feature is available only when you select the 256-bit AXI data width mode.

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