Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

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ID 683174
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Power Analysis 2. Power Optimization 3. Power Analysis and Optimization Document Archive A. Intel® Quartus® Prime Pro Edition User Guides
1. Power Analysis x
1.1. Power Analysis Tools 1.2. Running the Power Analyzer 1.3. Specifying Power Analyzer Input 1.4. Viewing Power Analysis Reports 1.5. Power Analysis in Modular Design Flows 1.6. Scripting Support 1.7. Power Analysis Revision History
1.3. Specifying Power Analyzer Input x
1.3.1. Settings for Power Analysis 1.3.2. Specifying Signal Activity Data 1.3.3. Specifying the Default Toggle Rate 1.3.4. Specifying Toggle Rates for Specific Nodes 1.3.5. Avoiding Simulation Node Name Match
1.3.2. Specifying Signal Activity Data x
1.3.2.1. Using Simulation Signal Activity Data in Power Analysis 1.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 1.3.2.3. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 1.3.2.4. Signal Activities from User Defaults Only
1.3.2.1. Using Simulation Signal Activity Data in Power Analysis x
1.3.2.1.1. Generating Signal Activity Data for Power Analysis 1.3.2.1.2. Generating Standard Delay Output for Power Analysis 1.3.2.1.3. Simulation Glitch Filtering
1.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation x
1.3.2.2.1. RTL Simulation Limitation
1.3.4. Specifying Toggle Rates for Specific Nodes x
1.3.4.1. Clock Node Toggle Rates
1.5. Power Analysis in Modular Design Flows x
1.5.1. Complete Design Simulation Power Analysis Flow 1.5.2. Modular Design Simulation Power Analysis Flow 1.5.3. Multiple Simulation Power Analysis Flow 1.5.4. Overlapping Simulation Power Analysis Flow 1.5.5. Partial Design Simulation Power Analysis Flow 1.5.6. Vectorless Estimation Power Analysis Flow
1.5.5. Partial Design Simulation Power Analysis Flow x
1.5.5.1. Specifying Start and End Time for Signal Activity Calculations
1.6. Scripting Support x
1.6.1. Running the Power Analyzer from the Command–Line
2. Power Optimization x
2.1. Factors Affecting Power Consumption 2.2. Design Space Explorer II for Power-Driven Optimization 2.3. Power-Driven Compilation 2.4. Design Guidelines 2.5. Power Optimization Advisor 2.6. Power Optimization Revision History
2.1. Factors Affecting Power Consumption x
2.1.1. Design Activity and Power Analysis 2.1.2. Device Selection 2.1.3. Environmental Conditions 2.1.4. Device Resource Usage 2.1.5. Signal Activity
2.1.4. Device Resource Usage x
2.1.4.1. Number, Type, and Loading of I/O Pins 2.1.4.2. Number and Type of Hard Logic Blocks 2.1.4.3. Number and Type of Global Signals
2.1.5. Signal Activity x
2.1.5.1. Toggle Rate 2.1.5.2. Static Probability
2.3. Power-Driven Compilation x
2.3.1. Power-Driven Synthesis 2.3.2. Power-Driven Fitter 2.3.3. Area-Driven Synthesis 2.3.4. Gate-Level Register Retiming 2.3.5. Intel® Quartus® Prime Compiler Settings 2.3.6. Assignment Editor Options
2.3.1. Power-Driven Synthesis x
2.3.1.1. Memory Block Optimization 2.3.1.2. Power-Aware Logic Mapping 2.3.1.3. Power-Aware Memory Balancing
2.4. Design Guidelines x
2.4.1. Clock Power Management 2.4.2. Pipelining and Retiming 2.4.3. Architectural Optimization 2.4.4. I/O Power Guidelines 2.4.5. Dynamically Controlled On-Chip Terminations (OCT) 2.4.6. Memory Optimization (M20K/MLAB) 2.4.7. DDR Memory Controller Settings 2.4.8. DSP Implementation 2.4.9. Reducing High-Speed Tile (HST) Usage 2.4.10. Unused Transceiver Channels 2.4.11. Periphery Power reduction XCVR Settings
2.4.1. Clock Power Management x
2.4.1.1. Clock Enable in Memory Blocks 2.4.1.2. LAB Clock Power 2.4.1.3. Clock Enables 2.4.1.4. Global Signals 2.4.1.5. Merge Clocks
2.4.1.2. LAB Clock Power x
2.4.1.2.1. LAB-Wide Clock Enable Example
2.4.1.4. Global Signals x
2.4.1.4.1. Viewing Clock Details in the Chip Planner
2.4.6. Memory Optimization (M20K/MLAB) x
2.4.6.1. Implementation 2.4.6.2. Rd/Wr Enables
2.4.11. Periphery Power reduction XCVR Settings x
2.4.11.1. Transceiver Settings 2.4.11.2. I/O Current Strength
2.5. Power Optimization Advisor x
2.5.1. Set Realistic Timing Constraints 2.5.2. Appropriate Device Family 2.5.3. Dynamic Power 2.5.4. Static Power 2.5.5. Appropriate I/O Standards 2.5.6. Use RAM Blocks 2.5.7. Shut Down RAM Blocks 2.5.8. Clock Enables on Logic 2.5.9. Pipeline Logic to Reduce Glitching
2.5.1. Set Realistic Timing Constraints x
2.5.1.1. Find Timing Information
1. Power Analysis
2. Power Optimization
3. Power Analysis and Optimization Document Archive
A. Intel® Quartus® Prime Pro Edition User Guides

2.6. Power Optimization Revision History

The following revision history applies to this chapter:

Table 13.  Document Revision History
Document Version Intel® Quartus® Prime Version Changes
2021.10.04 21.3.0 Modified the Compiler Settings topic.
2020.12.07 18.1.0 Added note to the Toggle Rate topic.
2019.08.02 18.1.0
  • Corrected typo in "Viewing Clock Details in the Chip Planner" topic.
  • Corrected typo in "Pipelining and Retiming" topic.
  • Corrected typo in "Implementation" topic.
  • Updated "DDR Memory Controller Settings" topic for latest IP name and to correct typos.
  • Corrected typo in "Pipeline Logic to Reduce Glitching" topic.
2018.09.24 18.1.0
  • Added topic: Factors Affecting Power Consumption, moved from chapter: Power Analysis
  • Extended content about Power Optimization Advisor with a description of recommendations.
  • Added design guidelines: Memories (M20K/MLAB), DDR Memory Controller Settings, DSP Implementation, Reducing High-Speed Tile (HST) Usage, Unused Transceiver Channels, Periphery Power reduction XCVR Settings
  • Removed content referring to device families not supported in Intel Quartus Prime Pro Edition.
2018.06.11 18.0.0
  • Moved general information about the Design Space Explorer (DSE II) to the Design Optimization User Guide, left a section about using DSE II for Power-Driven Optimization.
2018.05.07 18.0.0
  • Moved general information about the Design Space Explorer (DSE II) to the Design Optimization User Guide, left a section about using DSE II for Power-Driven Optimization.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Removed statement of support for gate-level timing simulation.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
  • Updated screenshot for DSE II GUI.
  • Added information about remote hosts for DSE II.
2014.12.15 14.1.0
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
  • Updated DSE II GUI and optimization settings.
2014.06.30 14.0.0 Updated the format.
May 2013 13.0.0 Added a note to “Memory Power Reduction Example” on Qsys and SOPC Builder power savings limitation for on-chip memory block.
June 2012 12.0.0 Removed survey link.
November 2011 10.0.2 Template update.
December 2010 10.0.1 Template update.
July 2010 10.0.0
  • Was chapter 11 in the 9.1.0 release
  • Updated Figures 14-2, 14-3, 14-6, 14-18, 14-19, and 14-20
  • Updated device support
  • Minor editorial updates
November 2009 9.1.0
  • Updated Figure 11-1 and associated references
  • Updated device support
  • Minor editorial update
March 2009 9.0.0
  • Was chapter 9 in the 8.1.0 release
  • Updated for the Quartus II software release
  • Added benchmark results
  • Removed several sections
  • Updated Figure 13–1, Figure 13–17, and Figure 13–18
November 2008 8.1.0
  • Changed to 8½” × 11” page size
  • Changed references to altsyncram to RAM
  • Minor editorial updates
May 2008 8.0.0
  • Added support for Stratix IV devices
  • Updated Table 9–1 and 9–9
  • Updated “Architectural Optimization” on page 9–22
  • Added “Dynamically-Controlled On-Chip Terminations” on page 9–26
  • Updated “Referenced Documents” on page 9–29
  • Updated references
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