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1.3.2.1. Using Simulation Signal Activity Data in Power Analysis
1.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation
1.3.2.3. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities
1.3.2.4. Signal Activities from User Defaults Only
1.5.1. Complete Design Simulation Power Analysis Flow
1.5.2. Modular Design Simulation Power Analysis Flow
1.5.3. Multiple Simulation Power Analysis Flow
1.5.4. Overlapping Simulation Power Analysis Flow
1.5.5. Partial Design Simulation Power Analysis Flow
1.5.6. Vectorless Estimation Power Analysis Flow
2.4.1. Clock Power Management
2.4.2. Pipelining and Retiming
2.4.3. Architectural Optimization
2.4.4. I/O Power Guidelines
2.4.5. Dynamically Controlled On-Chip Terminations (OCT)
2.4.6. Memory Optimization (M20K/MLAB)
2.4.7. DDR Memory Controller Settings
2.4.8. DSP Implementation
2.4.9. Reducing High-Speed Tile (HST) Usage
2.4.10. Unused Transceiver Channels
2.4.11. Periphery Power reduction XCVR Settings
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2.4.1.5. Merge Clocks
Evaluate the possibility of merging clocks and PLLs in the design.
Design | 2clks & 2PLLs | 1 Clk & 1 PLL |
---|---|---|
Oc_dma_stamp25 |
6.079W | 5.46W |
- 2clks & 2PLLs
Clk1:350Mhz, Fanout 46788
Clk2: 365Mhz, Fanout 2450
- 1Clk & 1PLL
Merge clks
clk: 365Mhz, Fanout 51277