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1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives
5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide
2.1. Creating an EMIF Project
2.2. Generating and Configuring the EMIF IP
2.3. Generating the Synthesizable EMIF Design Example
2.4. Generating the EMIF Design Example for Simulation
2.5. Simulation Versus Hardware Implementation
2.6. Simulating External Memory Interface IP With ModelSim
2.7. Pin Placement for Intel® Agilex™ 7 F-Series and I-Series EMIF IP
2.8. Compiling and Programming the Intel® Agilex™ 7 F-Series and I-Series EMIF Design Example
2.9. Generating a Design Example with the Calibration Debug Option
2.10. Generating a Design Example with the TG Configuration Option
2.11. Using the Design Example with the EMIF Debug Toolkit
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1.1. Release Information
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP Version | 2.7.0 |
Intel® Quartus® Prime | 23.1 |
Release Date | 2023.04.03 |