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1.1. 50GbE Supported Features
The 50GbE is designed to the 25G & 50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and designed to the IEEE 802.3by 25Gb Ethernet specification, as well as the IEEE 802.3ba-2012 High Speed Ethernet Standard available on the IEEE website (www.ieee.org). The MAC provides RX cut-through frame processing to optimize latency. The IP supports the following features:
- PHY features:
- Soft PCS logic that interfaces seamlessly to Intel® Arria® 10 FPGA 25.78125 gigabits per second (Gbps) serial transceivers.
- Frame structure control features:
- Support for jumbo packets, defined as packets greater than 1500 bytes.
- Receive (RX) CRC removal and pass-through control.
- Transmit (TX) CRC generation.
- RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
- TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.
- Frame monitoring and statistics:
- RX CRC checking and error reporting.
- Optional RX strict SFD checking per IEEE specification.
- RX malformed packet checking per IEEE specification.
- Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
- Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.
- Debug and testability features:
- Programmable serial PMA local loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
- Optional access to Native PHY Debug Master Endpoint (NPDME) for serial link debugging or monitoring PHY signal integrity.
- User system interfaces:
- Avalon® memory-mapped management interface to access the IP control and status registers.
- Avalon® streaming data path interface connects to client logic.
- Ready latency of 0 clock cycles for Avalon® -ST TX interface.
- Hardware and software reset control.
For a detailed specification of the Ethernet protocol refer to the IEEE 802.3 Ethernet Standard.
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