50 Gbps Ethernet IP Core User Guide

Download PDF
ID 683158
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the 50GbE Core 2. Getting Started 3. 50GbE Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control and Status Register Descriptions 8. Debugging the Link 9. Document Revision History
1. About the 50GbE Core x
1.1. 50GbE Supported Features 1.2. 50GbE Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization
1.2. 50GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 50GbE Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 50GbE Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Intel® Arria® 10 Devices 2.5.4. Placement Settings for the 50GbE Core
4. Functional Description x
4.1. 50GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 50GbE Core Functional Description x
4.1.1. 50GbE Core TX MAC Datapath 4.1.2. 50GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. 50 GbE RX PCS
4.1.1. 50GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion
4.1.2. 50GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. IP Core Malformed Packet Handling 4.1.2.4. Length/Type Field Processing 4.1.2.5. RX CRC Checking and Dynamic Forwarding
4.1.2.4. Length/Type Field Processing x
4.1.2.4.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals
7. Control and Status Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers
1. About the 50GbE Core
2. Getting Started
3. 50GbE Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control and Status Register Descriptions
8. Debugging the Link
9. Document Revision History

6.1. TX MAC Interface to User Logic

The TX MAC provides an Avalon® streaming interface to the FPGA fabric. The minimum packet size is nine bytes.
Table 11.   Avalon® Streaming TX DatapathAll interface signals are clocked by the clk_txmac clock.

Signal

Direction

Description

clk_txmac Output Clock for the TX logic. Derived from pll_refclk, and is an output from the 50GbE core. clk_txmac is guaranteed to be stable when tx_lanes_stable is asserted. The frequency of this clock is 390.625 MHz.All TX MAC interface signals are synchronous to clk_txmac.
l2_tx_data[127:0] Input

Data Input to MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order.

The 50GbE core does not process incoming frames of less than nine bytes correctly. You must ensure such frames do not reach the TX client interface.

You must send each TX data packet without intermediate idle cycles. Therefore, you must ensure your application can provide the data for a single packet in consecutive clock cycles. If data might not be available otherwise, you must buffer the data in your design and wait to assert l2_tx_startofpacket when you are assured the packet data to send on l2_tx_data[127:0] is available or will be available on time.

l2_tx_preamble[63:0] Input

User preamble data. Available when you select PREAMBLE PASS-THROUGH mode.

User logic drives the custom preamble data when l2_tx_startofpacket is asserted.
l2_tx_valid Input When asserted, indicates valid data is available on l2_tx_data[127:0]. You must assert this signal continuously between the assertions of l2_tx_startofpacket and l2_tx_endofpacket for the same packet.
l2_tx_startofpacket Input When asserted, indicates the first byte of a frame. When l2_tx_startofpacket is asserted, the MSB of l2_tx_data drives the first byte of the packet.
l2_tx_endofpacket Input When asserted, indicates the end of a packet. The IP core ignores packets with length less than nine bytes.
l2_tx_empty[3:0]   Specifies the number of empty bytes on l2_tx_data when l2_tx_endofpacket is asserted.
l2_tx_ready Output When asserted, indicates that the MAC can accept the data.
l2_txstatus_valid Output When asserted, indicates that l2_txstatus_error[6:0] is driving valid data.
l2_txstatus_data[39:0] Output

Specifies information about the transmit frame. The following fields are defined:

  • [Bit 39]: When asserted, indicates a PFC frame
  • [Bit 38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
l2_txstatus_error[6:0] Output

Specifies the error type in the transmit frame. The following fields are defined:

  • Bits[6:3]: Reserved
  • Bit[2]: Payload length error
  • Bit[1]: Oversized frame
  • Bit[0]: Reserved
Figure 19. Client to 50GbE MAC Avalon® Streaming Interface The IP core expects data order in l2_tx_data is highest byte to lowest byte. The first byte of the destination address is on l2_tx_data[127:120] , 0xabe4233 . . . in this timing diagram.
Related Information
Level Two Title