50 Gbps Ethernet IP Core User Guide

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ID 683158
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the 50GbE Core 2. Getting Started 3. 50GbE Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control and Status Register Descriptions 8. Debugging the Link 9. Document Revision History
1. About the 50GbE Core x
1.1. 50GbE Supported Features 1.2. 50GbE Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization
1.2. 50GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 50GbE Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 50GbE Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Intel® Arria® 10 Devices 2.5.4. Placement Settings for the 50GbE Core
4. Functional Description x
4.1. 50GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 50GbE Core Functional Description x
4.1.1. 50GbE Core TX MAC Datapath 4.1.2. 50GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. 50 GbE RX PCS
4.1.1. 50GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion
4.1.2. 50GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. IP Core Malformed Packet Handling 4.1.2.4. Length/Type Field Processing 4.1.2.5. RX CRC Checking and Dynamic Forwarding
4.1.2.4. Length/Type Field Processing x
4.1.2.4.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals
7. Control and Status Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers
1. About the 50GbE Core
2. Getting Started
3. 50GbE Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control and Status Register Descriptions
8. Debugging the Link
9. Document Revision History

4.1.2. 50GbE Core RX MAC Datapath

The RX MAC receives Ethernet frames and forwards the payload with relevant header bytes to the client after performing some MAC functions on header bytes. The RX MAC processes all incoming valid frames.

Figure 10. Flow of Client Frame With Preamble Pass-Through Turned On This figure uses the following notational conventions:
  • <p> = payload size, which is arbitrarily large.
  • <s> = number of padding bytes (0–46).
Figure 11. Flow of Client Frame With Preamble Pass-Through Turned Off This figure uses the following notational conventions:
  • <p> = payload size, which is arbitrarily large.
  • <s> = number of padding bytes (0–46).
Figure 12. RX MAC Datapath

Section Content
IP Core Preamble Processing
IP Core Strict SFD Checking
IP Core Malformed Packet Handling
Length/Type Field Processing
RX CRC Checking and Dynamic Forwarding

Level Two Title