50 Gbps Ethernet IP Core User Guide

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ID 683158
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the 50GbE Core 2. Getting Started 3. 50GbE Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control and Status Register Descriptions 8. Debugging the Link 9. Document Revision History
1. About the 50GbE Core x
1.1. 50GbE Supported Features 1.2. 50GbE Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization
1.2. 50GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. 50GbE Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 50GbE Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Handling Potential Jitter in Intel® Arria® 10 Devices 2.5.4. Placement Settings for the 50GbE Core
4. Functional Description x
4.1. 50GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 50GbE Core Functional Description x
4.1.1. 50GbE Core TX MAC Datapath 4.1.2. 50GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. 50 GbE RX PCS
4.1.1. 50GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion
4.1.2. 50GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. IP Core Malformed Packet Handling 4.1.2.4. Length/Type Field Processing 4.1.2.5. RX CRC Checking and Dynamic Forwarding
4.1.2.4. Length/Type Field Processing x
4.1.2.4.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals
7. Control and Status Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers
1. About the 50GbE Core
2. Getting Started
3. 50GbE Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control and Status Register Descriptions
8. Debugging the Link
9. Document Revision History

6.2. RX MAC Interface to User Logic

The RX MAC provides an Avalon® streaming interface to the FPGA fabric. The datapath comprises 2, 64-bit words.
Table 12.   Avalon® Streaming RX Datapath All interface signals are clocked by the clk_rxmac clock.

Signal

Direction

Description

clk_rxmac Output Clock for the RX MAC. Recovered from the incoming data. This clock is guaranteed stable when rx_pcs_ready is asserted. The frequency of this clock is 390.625 MHz. All RX MAC interface signals are synchronous to clk_rxmac.
l2_rx_data[127:0] Output

Data output from the MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order. The IP core reverses the byte order to meet the requirements of the Ethernet standard.

l2_rx_preamble[63:0] Output

Received preamble data. Available when you select PREAMBLE PASS-THROUGH mode.

Valid when l2_rx_startofpacket is asserted.
l2_rx_valid Output When asserted, indicates that l2_rx_data[127:0] is driving data. The IP core need not assert this signal continuously between the assertions of l2_tx_startofpacket and l2_tx_endofpacket for the same packet. During alignment marker cycles, the IP core drives IDLE cycles.
l2_rx_startofpacket Output

When asserted, indicates the first byte of a frame.

In PREAMBLE PASS-THROUGH mode, marks the first byte of the preamble.

l2_rx_endofpacket Output When asserted, indicates the last data byte of a frame, before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position.
l2_rx_empty[3:0] Output Specifies the number of empty bytes when l2_rx_endofpacket is asserted.

The packet can end at any byte position. The empty bytes are the low-order bytes.

l2_rx_error[5:0] Output

When asserted in the same cycle as l2_rx_endofpacket, indicates the current packet should be treated as an error packet. The 6 bits of l2_rx_error specify the following errors:

  • l2_rx_error[5]: Unused.
  • l2_rx_error[4]: Payload length error. If the length field is <1535 bytes, the received payload length is less than what is advertised in payload length field.
  • l2_rx_error[3]: Oversized frame. The frame size is greater than the value specified in the RXMAC_SIZE_CONFIG register.
  • l2_rx_error[2]: Undersized frame – The frame size is less than 64 bytes. Frame size = header size + payload size.
  • l2_rx_error[1]: CRC Error. The computed CRC value differs from the received CRC.
  • l2_rx_error[0]: Malformed packet. The packet is terminated with a non-terminate control character. When this bit is asserted, l2_rx_error[1] is also asserted.
l2_rxstatus_valid Output When asserted, indicates that l2_rxstatus_data is driving valid data.
l2_rxstatus_data[39:0] Output

Specifies information about the received frame. The following fields are defined:

  • [Bit 39]: When asserted, indicates a PFC frame
  • [Bit 38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
Figure 20.  50GbE MAC to Client Avalon® Streaming Interface l2_rx_data reception order is highest byte to lowest byte. The first byte of the destination address is on l2_rx_data[127:120] , 0xabe42339 . . . in this timing diagram..
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