50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Public
Document Table of Contents

2.6. Compiling the Full Design and Programming the FPGA

You can use the Start Compilation command on the Processing menu in the Intel® Quartus® Prime software to compile your design. After successfully compiling your design, program the targeted Intel® FPGA with the Programmer and verify the design in hardware.

Note: The 50GbE core design example synthesis directories include Synopsys Constraint (.sdc) files that you can copy and modify for your own design.
Note: For additional .sdc file requirements, please refer to the KDB Answer at https://www.altera.com/support/support-resources/knowledge-base/tools/2017/fb470823.html.