Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

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ID 683152
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® HLS Compiler Pro Edition Best Practices Guide 2. Best Practices for Coding and Compiling Your Component 3. FPGA Concepts 4. Interface Best Practices 5. Loop Best Practices 6. fMAX Bottleneck Best Practices 7. Memory Architecture Best Practices 8. System of Tasks Best Practices 9. Datatype Best Practices 10. Advanced Troubleshooting A. Intel® HLS Compiler Pro Edition Best Practices Guide Archives B. Document Revision History for Intel® HLS Compiler Pro Edition Best Practices Guide
3. FPGA Concepts x
3.1. FPGA Architecture Overview 3.2. Concepts of FPGA Hardware Design 3.3. Methods of Hardware Design
3.1. FPGA Architecture Overview x
3.1.1. Adaptive Logic Module (ALM) 3.1.2. Digital Signal Processing (DSP) Block 3.1.3. Random-Access Memory (RAM) Blocks
3.1.1. Adaptive Logic Module (ALM) x
3.1.1.1. Lookup Table (LUT) 3.1.1.2. Register
3.2. Concepts of FPGA Hardware Design x
3.2.1. Maximum Frequency (fMAX) 3.2.2. Latency 3.2.3. Pipelining 3.2.4. Throughput 3.2.5. Datapath 3.2.6. Control Path 3.2.7. Occupancy
3.3. Methods of Hardware Design x
3.3.1. How Source Code Becomes a Custom Hardware Datapath 3.3.2. Scheduling 3.3.3. Mapping Parallelism Models to FPGA Hardware 3.3.4. Memory Types
3.3.1. How Source Code Becomes a Custom Hardware Datapath x
3.3.1.1. Mapping Source Code Instructions to Hardware 3.3.1.2. Mapping Arrays and Their Accesses to Hardware
3.3.2. Scheduling x
3.3.2.1. Dynamic Scheduling 3.3.2.2. Clustering the Datapath 3.3.2.3. Handshaking Between Clusters
3.3.3. Mapping Parallelism Models to FPGA Hardware x
3.3.3.1. Data Parallelism 3.3.3.2. Task Parallelism
3.3.3.1. Data Parallelism x
3.3.3.1.1. Executing Independent Operations Simultaneously 3.3.3.1.2. Pipelining
3.3.3.1.2. Pipelining x
3.3.3.1.2.1. Pipelining Loops Within A Component 3.3.3.1.2.2. Pipelining Across Component Invocations
3.3.4. Memory Types x
3.3.4.1. Component Memory 3.3.4.2. External Memory
4. Interface Best Practices x
4.1. Choose the Right Interface for Your Component 4.2. Control LSUs For Your Variable-Latency MM Host Interfaces 4.3. Avoid Pointer Aliasing
4.1. Choose the Right Interface for Your Component x
4.1.1. Pointer Interfaces 4.1.2. Avalon® Memory Mapped Host Interfaces 4.1.3. Avalon® Memory Mapped Agent Memories 4.1.4. Avalon® Memory Mapped Agent Registers 4.1.5. Avalon® Streaming Interfaces 4.1.6. Pass-by-Value Interface
5. Loop Best Practices x
5.1. Reuse Hardware By Calling It In a Loop 5.2. Parallelize Loops 5.3. Construct Well-Formed Loops 5.4. Minimize Loop-Carried Dependencies 5.5. Avoid Complex Loop-Exit Conditions 5.6. Convert Nested Loops into a Single Loop 5.7. Place if-Statements in the Lowest Possible Scope in a Loop Nest 5.8. Declare Variables in the Deepest Scope Possible 5.9. Raise Loop II to Increase fMAX 5.10. Control Loop Interleaving
5.2. Parallelize Loops x
5.2.1. Pipeline Loops 5.2.2. Unroll Loops 5.2.3. Example: Loop Pipelining and Unrolling
6. fMAX Bottleneck Best Practices x
6.1. Balancing Target fMAX and Target II
7. Memory Architecture Best Practices x
7.1. Example: Overriding a Coalesced Memory Architecture 7.2. Example: Overriding a Banked Memory Architecture 7.3. Merge Memories to Reduce Area 7.4. Example: Specifying Bank-Selection Bits for Local Memory Addresses
7.3. Merge Memories to Reduce Area x
7.3.1. Example: Merging Memories Depth-Wise 7.3.2. Example: Merging Memories Width-Wise
8. System of Tasks Best Practices x
8.1. Executing Multiple Loops in Parallel 8.2. Sharing an Expensive Compute Block 8.3. Implementing a Hierarchical Design 8.4. Balancing Capacity in a System of Tasks
8.4. Balancing Capacity in a System of Tasks x
8.4.1. Enable the Intel® HLS Compiler to Infer Data Path Buffer Capacity Requirements 8.4.2. Explicitly Add Buffer Capacity to Your Design When Needed
9. Datatype Best Practices x
9.1. Avoid Implicit Data Type Conversions 9.2. Avoid Negative Bit Shifts When Using the ac_int Datatype
10. Advanced Troubleshooting x
10.1. Component Fails Only In Simulation 10.2. Component Gets Poor Quality of Results
1. Intel® HLS Compiler Pro Edition Best Practices Guide
2. Best Practices for Coding and Compiling Your Component
3. FPGA Concepts
4. Interface Best Practices
5. Loop Best Practices
6. fMAX Bottleneck Best Practices
7. Memory Architecture Best Practices
8. System of Tasks Best Practices
9. Datatype Best Practices
10. Advanced Troubleshooting
A. Intel® HLS Compiler Pro Edition Best Practices Guide Archives
B. Document Revision History for Intel® HLS Compiler Pro Edition Best Practices Guide

B. Document Revision History for Intel® HLS Compiler Pro Edition Best Practices Guide

Document Version Intel® HLS Compiler Pro Edition Version Changes
2021.10.04 21.3
  • Maintenance release.
2021.06.21 21.2
  • Revised references to Avalon Interfaces to align with new Avalon Interconnect terminology. Avalon master interfaces are now Avalon host interfaces, and Avalon slave interfaces are now Avalon agent interfaces.
2021.03.29 21.1
2020.12.14 20.4
2020.09.28 20.3
2020.06.22 20.2
2020.04.13 20.1
2020.01.27 19.4
2019.12.16 19.4
  • Removed information about Intel® HLS Compiler Standard Edition.

    For best practices information for the Intel® HLS Compiler Standard Edition, see Intel® HLS Compiler Standard Edition Best Practices Guide .

  • Added information to Example: Specifying Bank-Selection Bits for Local Memory Addresses to explain the difference between the element-address bank-selection bits selected with the hls_bankbits attribute and the byte- address bank-selection bits reported in the Function Memory Viewer in the High-Level Design Reports.
  • References to the Component Viewer have been replaced with references to the Function View of the Graph Viewer.
  • Reference to the Component Memory Viewer have been replaced with references to the Function Memory Viewer.

Document Revision History for Intel® HLS Compiler Best Practices Guide

Previous versions of the Intel® HLS Compiler Best Practices Guide contained information for both Intel® HLS Compiler Standard Edition and Intel® HLS Compiler Pro Edition.

Document Version Intel® Quartus® Prime Version Changes
2019.09.30 19.3
2019.07.01 19.2
  • Maintenance release.
2019.04.01 19.1
2018.12.24 18.1
  • Updated to Loop Best Practices to include information about function inlining in components and using loops to minimize the resulting hardware duplication.
2018.09.24 18.1
2018.07.02 18.0
  • Added a new chapter, Advanced Troubleshooting, to help you troubleshoot when your component behaves differently in simulation and emulation, and when your component has unexpectedly poor performance, resource utilization, or both.
2018.05.07 18.0
  • Starting with Intel® Quartus® Prime Version 18.0, the features and devices supported by the Intel® HLS Compiler depend on what edition of Intel® Quartus® Prime you have. Intel® HLS Compiler publications now use icons to indicate content and features that apply only to a specific edition as follows:
    Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Pro Edition.
    Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Standard Edition.
  • Added best_practices/loop_coalesce to the list of tutorials in Loop Best Practices.
  • Added interfaces/explicit_streams_packets_ready_empty to list of tutorials in Interface Best Practices.
  • Revised Example: Specifying Bank-Selection Bits for Local Memory Addresses with improved descriptions and new graphics that reflect what you would see in the high-level design reports (report.html) for the example component.
  • Updated Example: Overriding a Coalesced Memory Architecture with new images to show the memory structures as well as how the FPGA resource usage differs between the two components
2017.12.22 17.1.1
2017.11.06 17.1 Initial release.

Parts of this book consist of content previously found in the Intel® High Level Synthesis Compiler User Guide and the Intel® High Level Synthesis Compiler Reference Manual.

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