Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide: For Intel® Stratix® 10 Devices

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ID 683147
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.4
IP Version 1.0.0
The Low Latency 50G Ethernet Intel FPGA IP core provides a design example which allows you to:
  • Compile the design — to get an estimate IP core area and timing
  • Simulate the design — to verify the IP core functionality through simulation
  • Test the design on hardware — to test the design on the Intel® Stratix® 10 Transceiver Signal Integrity Development Kit
When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Steps for the Design Example

Section Content
Directory Structure
Simulation Design Example Components
Hardware Design Example Components
Generating the Design
Simulating the Design Example Testbench
Compiling and Configuring the Design Example in Hardware
Testing the Hardware Design Example

Level Two Title