Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide: For Intel® Stratix® 10 Devices

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ID 683147
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

1.7. Testing the Hardware Design Example

After you compile the Low Latency 50G Ethernet IP core design example and configure it on your Intel® Stratix® 10 device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

To turn on the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Intel® Stratix® 10 device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
  3. Type source main.tcl to open a connection to the JTAG master.

You can program the IP core with the following design example commands:

  • chkphy_status: Displays the clock frequencies and PHY lock status.
  • chkmac_stats: Displays the values in the MAC statistics counters.
  • clear_all_stats: Clears the IP core statistics counters.
  • start_pkt_gen: Starts the packet generator.
  • stop_pkt_gen: Stops the packet generator.
  • loop_on: Turns on internal serial loopback
  • loop_off: Turns off internal serial loopback.
  • reg_read <addr>: Returns the IP core register value at <addr>.
  • reg_write <addr> <data>: Writes <data> to the IP core register at address <addr>.
The successful test run displays output confirming the following behavior:
  1. Turning off packet generation
  2. Enabling loopback
  3. Waiting for RX clock to settle
  4. Printing PHY status
  5. Clearing MAC statistics counters
  6. Sending packets
  7. Reading MAC statistics counters
  8. Printing MAC statistics counters, which show 0 in all error counters
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