Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide: For Intel® Stratix® 10 Devices

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ID 683147
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

1.4. Generating the Design

Figure 5. Procedure
Figure 6. Example Design Tab in the Low Latency 50G Ethernet Parameter Editor

Follow these steps to generate the Low Latency 50G Ethernet hardware design example and testbench:

  1. If you do not already have an Intel® Quartus® Prime Pro Edition project in which to integrate your Low Latency 50G Ethernet core, you must create one.
    1. In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
    2. Specify the device family Intel Stratix 10 and select a device that meets all of these requirements:
      • Transceiver tile is L-tile or H-tile (any transceiver tile)
      • Transceiver speed grade is –1 or –2
      • Core speed grade is –1 or –2
      • Production version devices
      • Device is not an 1SG280L ES1 device (part name 1SG280L...VGS1)
    3. Click Finish.
  2. In the IP Catalog, locate and select Low Latency 50G Ethernet . The New IP Variation window appears.
  3. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, specify the parameters for your IP core variation.
    The Low Latency 50G Ethernet design example is not available for the following selections:
    • Enable MAC Flow Control
    • Enable TX CRC insertion
    • Enable preamble passthrough
  6. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only and hardware design examples.
    Note: You must select at least one of the Simulation and Synthesis options to generate the design example.
  7. On the Example Design tab, under Generated HDL Format, select the file format.
  8. Under Target Development Kit select the Stratix 10 Transceiver Signal Integrity Development Kit, or None.
    Note: When you select Stratix 10 Transceiver Signal Integrity Development Kit as the Target Development Kit, the design example is generated based on a specific device and it overwrites the device you selected in your project file. If you select None as the Target Development Kit, ensure the device you selected is the correct device and make changes to the pins assignment in the.qsf file. By default, the .qsf file is generated based on the device used in Intel Stratix 10 Transceiver Signal Integrity Development Kit.
  9. Click the Generate Example Design button. The Select Example Design Directory window appears.
  10. If you want to modify the design example directory path or name from the defaults displayed (alt_e50s10_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
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