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Release Information for GPIO Intel® FPGA IP
GPIO Intel® FPGA IP Features
GPIO Intel® FPGA IP Data Paths
GPIO Intel® FPGA IP Interface Signals
Verifying Resource Utilization and Design Performance
GPIO Intel® FPGA IP Parameter Settings
Register Packing
GPIO Intel® FPGA IP Timing
GPIO Intel® FPGA IP Design Examples
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
Intel® Arria® 10 and Intel® Cyclone® 10 GX GPIO Intel® FPGA IP User Guide Archives
Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Data Bit-Order for Data Interface
Figure 9. Data Bit-Order ConventionThis figure shows the bit-order convention for the din, dout and oe data signals.
- If the data bus size value is SIZE, the LSB is at the right-most position.
- If the data bus size value is 2 × SIZE, the bus is made of two words of SIZE.
- If the data bus size value is 4 × SIZE, the bus is made of four words of SIZE.
- The LSB is in the right-most position of each word.
- The right-most word specifies the first word going out for output buses and the first word coming in for input buses.
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